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參數(shù)資料
| 型號： | M34501E4FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 4.4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, SOP-20 |
| 文件頁數(shù)： | 174/213頁 |
| 文件大小： | 3014K |
| 代理商： | M34501E4FP |
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1-50
HARDWARE
4501 Group User’s Manual
LIST OF PRECAUTIONS
Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
connect a bypass capacitor (approx. 0.1
F) between pins VDD
and VSS at the shortest distance,
equalize its wiring in width and length, and
use relatively thick wire.
In the One Time PROM version, CNVSS pin is also used as VPP
pin. Accordingly, when using this pin, connect this pin to VSS
through a resistor about 5 k
(connect this resistor to CNVSS/
VPP pin as close as possible).
Register initial values 1
The initial value of the following registers are undefined after sys-
tem is released from reset. After system is released from reset,
set initial values.
Register Z (2 bits)
Register D (3 bits)
Register E (8 bits)
Register initial values 2
The initial value of the following registers are undefined at RAM
back-up. After system is returned from RAM back-up, set initial
values.
Register Z (2 bits)
Register X (4 bits)
Register Y (4 bits)
Register D (3 bits)
Register E (8 bits)
Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are eight identical registers, so that subrou-
tines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction. Accord-
ingly, be careful not to over the stack when performing these
operations together.
Prescaler
Stop the prescaler operation to change its frequency dividing ra-
tio.
Timer count source
Stop timer 1 or 2 counting to change its count source.
Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2
instruction to read its data.
Writing to the timer
Stop timer 1 or 2 counting and then execute the T1AB or T2AB
instruction to write its data.
Writing to reload register R1
When writing data to reload register R1 while timer 1 is operat-
ing, avoid a timing when timer 1 underflows.
10
11
12
13
Watchdog timer
The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function, execute
the DWDT instruction and the WRST instruction continuously,
and clear the WEF flag to “0” to stop the watchdog timer function.
The watchdog timer function is valid after system is returned from
the RAM back-up. When not using the watchdog timer function,
execute the DWDT instruction and the WRST instruction continu-
ously every system is returned from the RAM back-up, and stop
the watchdog timer function.
Multifunction
The input/output of D2, D3, P12 and P13 can be used even when
C, K, CNTR (input) and INT are selected.
The input of P12 can be used even when CNTR (output) is selected.
The input/output of P20 and P21 can be used even when AIN0 and
AIN1 are selected.
Program counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
POF and POF2 instructions
When the POF or POF2 instruction is executed continuously af-
ter the EPOF instruction, system enters the RAM back-up state.
Note that system cannot enter the RAM back-up state when ex-
ecuting only the POF or POF2 instruction.
Be sure to disable interrupts by executing the DI instruction be-
fore executing the EPOF instruction and the POF or POF2
instruction continuously.
P13/INT pin
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 47)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
after executing at least one instruction (refer to Figure 47).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 47).
LA
4
; (02)
TV1A
; The SNZ0 instruction is valid ...........
LA
8
; (12)
TI1A
; Control of INT pin input is changed
NOP
...........................................................
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 47 External 0 interrupt program example-1
14
LIST OF PRECAUTIONS
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相關(guān)代理商/技術(shù)參數(shù) |
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