
deveopmen
UARTi Special Mode Register
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
192
IICM2 = 0
Acknowledge not detect
(NACK)
Acknowledge detect (ACK)
Acknowledge detect (ACK)
Rising edge of the last bit of re-
ceive clock
Rising edge of the last bit of re-
ceive clock
Function
Interrupt no. 17, 19, 33, 35, 37 fac-
tor
Interrupt no. 18, 20, 34, 36, 38 fac-
tor
DMA factor
Data transfer timing from UART re-
ceive shift register to receive buffer
UART receive / ACK interrupt re-
quest generation timing
IICM2 = 1
UARTi transfer (rising edge of the
last bit)
UARTi receive (falling edge of the
last bit)
UARTi receive (falling edge of the
last bit)
Rising edge of the last bit of re-
ceive clock
Rising edge of the last bit of re-
ceive clock
Set up time
Hold time
SCL
SDA
(Start condition)
SDA
(Stop condition)
UARTi Special Mode Register 3 (UiSMR3:Addresses 0365
16
, 02E5
16
, 0335
16
, 0325
16
, 02F5
16
)
Bit 1 is clock phase set bit (CKPH). When both the IIC mode select bit (bit 0 of UARTi special mode
select register) and the IIC mode select bit 2 (bit 0 of UiSMR2 register) are "1", functions changed by
these bits are shown in table 1.21.3 and figure 1.21.4.
Bits 5 to 7 are SDAi digital delay setting bits (DL0 to DL2). By setting these bits, it is possible to turn the
SDAi delay OFF or set the BRG count source delay to 2 to 8 cycles.
Table 1.21.3. Functions changed by clock phase set bits
Function
CKPH = 0, IICM = 1, IICM2 = 1
Initial value = H, last value = L
Rising edge of 9th bit
Falling edge of 9th bit
SCL initial and last value
Transfer interrupt factor
Data transfer times from UART re-
ceive shift register to receive buffer
register
CKPH = 1, IICM = 1, IICM2 = 1
Initial value = L, last value = L
Falling edge of 10th bit
Two times :falling edge of 9th bit
and rising edge of 9th bit
Table 1.21.2. Functions changed by I
2
C mode select bit 2
Figure 1.21.3. Start/stop condition detect timing characteristics
3 to 6 cycles < set up time
(Note)
3 to 6 cycles < hold time
(Note)
Note : Cycle number shows main clock input oscillation frequency f(X
IN
) cycle number.