
11
32176 Group
Mitsubishi Microcomputers
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Under Development
Jan. 30, 2003
Rev.1.4
Outline of the CPU core
The M32176 Group uses the M32R RISC CPU core, and has
an instruction set which is common to all microcomputers in the
M32R family.
Instructions are processed in five pipelined stages consist-
ing of instruction fetch, decode, execution, memory access,
and write back. Thanks to its “out-of-order-completion”
mechanism, the M32R CPU allows for clock cycle efficient,
instruction execution control.
The M32R CPU internally contains sixteen 32-bit general-
purpose registers. The instruction set consists of 83 discrete
instructions, which come in either 16-bit or 32-bit instruction
format. Use of the 16-bit instruction format helps to reduce
the program code size. Also, the availability of 32-bit instruc-
tions facilitates programming and increases the perfor-
mance at the same clock speed, as compared to architec-
tures with segmented address spaces.
Multiply-Accumulate instructions comparable to
DSP
The M32R CPU contains a multiplier/accumulator that can
execute 32-bit × 16-bit in one cycle. Therefore, it executes a
32-bit × 32-bit integer multiplication instruction in three cycles.
Also, the M32R CPU supports the following four multiply-
Accumulate instructions (or multiplication instructions) for
DSP function use.
(1) 16 high-order register bits × 16 high-order register bits
(2) 16 low-order register bits × 16 low-order register bits
(3) All 32 register bits × 16 high-order register bits
(4) All 32 register bits × 16 low-order register bits
Furthermore, the M32R CPU has instructions for rounding
the value stored in the accumulator to 16 or 32-bit, and in-
structions for shifting the accumulator value to adjust digits
before storing in a register. Because these instructions also
can be executed in one cycle, DSP comparable data pro-
cessing capability can be obtained by using them in combi-
nation with high-speed data transfer instructions such as
Load & Address Update or Store & Address Update.
Three operation modes
The M32176 Group has three operation modes: single-chip
mode, external extended mode,and processor mode. These
operation modes are changed from one to another by set-
ting the MOD0 and MOD1 pins.
Address space
The 32176 Group’s logical address is always handled in
width of 32-bit, providing a linear address space of up to 4G
bytes. The 32176’s address space is divided into the follow-
ing spaces.
User space
A 2G-byte area from H’0000 0000 to H’7FFF FFFF is the
user space. Located in this space are the user ROM area,
external extended area, internal RAM area, and SFR (Spe-
cial Function Register) area (internal peripheral I/O regis-
ters). Of these, the user ROM area and external extended
area are located differently depending on mode settings.
System space
A 2G-byte area from H’8000 0000 to H’FFFF FFFF is the
system area. This space is reserved for use by development
tools such as an in-circuit emulator and debug monitor, and
cannot be used by the user.