參數(shù)資料
型號(hào)： M32172F2VFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, PLASTIC, LQFP-144
文件頁(yè)數(shù)： 40/40頁(yè)
文件大?。?/td> 3556K
代理商： M32172F2VFP
8.3 Input/Output Port Related Registers ....................................................................... 8-6
8.3.1 Port Data Registers ............................................................................. 8-8
8.3.2 Port Direction Registers ...................................................................... 8-9
8.3.3 Port Operation Mode Registers ........................................................... 8-10
8.4 Port Peripheral Circuits .......................................................................................... 8-31
8.5 Precautions on Input/Output Ports ......................................................................... 8-39
CHAPTER 9 DMAC
9.1 Outline of DMAC .................................................................................................... 9-2
9.2 DMAC Related Registers ....................................................................................... 9-5
9.2.1 DMA Channel Control Registers ........................................................ 9-7
9.2.2 DMA Request Extended Cause Register ........................................... 9-18
9.2.3 DMA Software Request Generation Registers ................................... 9-29
9.2.4 DMA Source Address Registers ......................................................... 9-30
9.2.5 DMA Destination Address Registers .................................................. 9-31
9.2.6 DMA Transfer Count Registers .......................................................... 9-32
9.2.7 DMA Interrupt Request Status Registers ........................................... 9-33
9.2.8 DMA Interrupt Mask Registers ........................................................... 9-35
9.3 Functional Description of DMAC ............................................................................ 9-39
9.3.1 Cause of DMA Request ...................................................................... 9-39
9.3.2 DMA Transfer Processing Procedure ................................................. 9-49
9.3.3 Starting DMA ...................................................................................... 9-50
9.3.4 Priority of DMA Channels ................................................................... 9-50
9.3.5 Gaining and Releasing Control of the Internal Bus ............................ 9-51
9.3.6 Transfer Unit ....................................................................................... 9-51
9.3.7 Transfer Count ................................................................................... 9-51
9.3.8 Address Space ................................................................................... 9-52
9.3.9 Transfer Operation ............................................................................. 9-52
9.3.10 End of DMA and Interrupt ................................................................. 9-55
9.3.11 Register Status after End of DMA Transfer ...................................... 9-55
9.4 Precautions on Using DMAC ................................................................................. 9-56
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