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參數(shù)資料
| 型號(hào)： | M32172F2VFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 37/40頁 |
| 文件大?。?/td> | 3556K |
| 代理商： | M32172F2VFP |
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2.6 Data Formats ......................................................................................................... 2-7
2.6.1 Data Types ............................................................................................... 2-7
2.6.2 Data Formats ............................................................................................ 2-8
CHAPTER 3 ADDRESS SPACE
3.1 Outline of the Address Space ................................................................................. 3-2
3.2 Operation Modes .................................................................................................... 3-5
3.3 Internal ROM and External Extended Areas ........................................................... 3-8
3.3.1 Internal ROM Area .............................................................................. 3-8
3.3.2 External Extended Area ...................................................................... 3-8
3.4 Internal RAM and SFR Areas ................................................................................. 3-9
3.4.1 Internal RAM Area ............................................................................... 3-9
3.4.2 SFR (Special Function Register) Area ................................................ 3-9
3.5 EIT Vector Entry ..................................................................................................... 3-35
3.6 ICU Vector Table .................................................................................................... 3-36
3.7 Precautions on Address Space .............................................................................. 3-38
CHAPTER 4 EIT
4.1 Outline of EIT .......................................................................................................... 4-2
4.2 EIT Events .............................................................................................................. 4-3
4.2.1 Exceptions ........................................................................................... 4-3
4.2.2 Interrupts ............................................................................................. 4-3
4.2.3 Trap ..................................................................................................... 4-3
4.3 EIT Processing Procedure ...................................................................................... 4-4
4.4 EIT Processing Mechanism .................................................................................... 4-6
4.5 Accepting EIT Events ............................................................................................. 4-7
4.6 Saving and Restoring PC and PSW ....................................................................... 4-8
4.7 EIT Vector Entry ..................................................................................................... 4-10
4.8 Exception Handling ................................................................................................. 4-11
4.8.1 Reserved Instruction Exception (RIE) ................................................. 4-11
4.8.2 Address Exception (AE) ...................................................................... 4-13
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