參數(shù)資料
型號: M32172F2VFP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, PLASTIC, LQFP-144
文件頁數(shù): 15/40頁
文件大?。?/td> 3556K
代理商: M32172F2VFP
1
1-2
Rev.1.0
1.1 Overview
1.1.1 M32R Family CPU Core
(1) Uses the RISC architecture
The 32172/32173 are 32-bit, RISC single-chip microcomputers built around the M32R family
CPU core (hereafter referred to as the "M32R") and incorporating flash memory, RAM, and
various other peripheral functions... all integrated into a single chip.
The M32R uses the RISC architecture. Memory accesses are performed using Load and Store
instructions, and various arithmetic operations are executed using register-to-register
operating instructions. The M32R internally has sixteen 32-bit general-purpose registers and a
total of 83 discrete instructions.
In addition to Load and Store instructions, the M32R supports compound instructions such as
Load & Address Update and Store & Address Update. These instructions are useful for
speeding up data transfers.
(2) 5-stage pipelined processing
The M32R uses 5-stage pipelined instruction processing consisting of Instruction Fetch,
Decode, Execute, Memory Access, and Write Back. Not just load and store instructions or
register-to-register operation instructions, compound instructions such as Load & Address
Update and Store & Address Update also are executed in one cycle.
Instructions are entered into the execution stage in the order they are fetched, but this does not
always mean that the first instruction entered is executed first. If the execution of a load or store
instruction entered earlier is delayed by one or more wait cycles inserted in memory access, a
register-to-register operation instruction entered later may be executed before said load or
store instruction. By using "out-of-order-completion" like this, the M32R controls instruction
execution without wasting clock cycles.
(3) Compact instruction code
Instructions of the M32R come in either a 16-bit instruction or a 32-bit instruction format. Use of
the 16-bit instruction format especially helps to reduce the code size of a program.
Some 32-bit instructions can branch directly to a location 32 Mbytes forward or backward from
the currently executed instruction address. The availability of such instructions makes
programming easier than for architectures with segmented address spaces.
Overview
1.1 Overview
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