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參數(shù)資料
| 型號： | M32000D4BFP-80 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 80 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 43/44頁 |
| 文件大?。?/td> | 448K |
| 代理商： | M32000D4BFP-80 |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
8
PIN DESCRIPTION (3/3)
type
pin name
name
I/O
function
bus
__
DC*
data complete
I/O
When the M32000D4BFP-80 drives an external bus cycle, it
control
__
automatically inserts wait cycles until DC is input by the slave
(cont.)
device in the system bus.
When the M32000D4BFP-80 is in the hold state and the internal
DRAM is accessed from an external bus master,the
__
M32000D4BFP-80 outputs DC to notify to the external bus master
that the bus cycle to the internal DRAM has been completed.
______
HREQ
hold
input
______
Bus right request input pin of the system bus. When HREQ is an
"L" level, the M32000D4BFP-80 switches to the hold state.
_____
HACK
hold
output
Indicates that the M32000D4BFP-80 has switched to the hold
acknowledge
state and releases the bus right of the system bus to the requestor.
__
CS
chip
input
Signal input to the M32000D4BFP-80 when it is in the hold state
select
to request access to the internal DRAM from an external bus
__
master. When an "L"level is input to CS, the M32000D4
BFP-80 accesses the internal DRAM at the address input via
the address pins.
interrupt
___
SBI
system
input
___
System break interrupt input pin. The SBI is not masked by the
IE bit in the PSW register. It is also used to return from CPU
sleep mode and to request the start of operation in slave mode.
___
INT
external
input
External interrupt request input pin. It is also used to return from
interrupt
CPU sleep mode and to request the start of operation the slave
mode.
programm-
PP0, PP1
port
I/O
Two programmable I/O ports.
able I/O port
* This pin goes to high-impedance in the hold state.
__
The DC pin becomes an output pin when the CS signal is input to the M32000D4BFP-80.
(Hi-Z)
break
interrupt
controller
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