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參數(shù)資料
| 型號： | M32000D4BFP-80 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 80 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 31/44頁 |
| 文件大小： | 448K |
| 代理商： | M32000D4BFP-80 |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
37
(3) Arbitration and external bus master read/write timing
Limits
Symbol
Test conditions
td(CLKIN-HACKHX)
td(CLKIN-HACKL)
td(CLKIN-HACKLX)
td(CLKIN-HACKH)
td(CLKIN-AZ)
td(CLKIN-AZX)
td(CLKIN-DZX)
td(CLKIN-DV)
td(CLKIN-DXZ)
td(CLKIN-DVX)
td(CS-DCZX)
td(CLKIN-DCHX)
td(CLKIN-DCL)
td(CLKIN-DCXZ)
td(CLKIN-DCLX)
42
43
44
45
46
47
54
55
56
57
58
59
60
61
62
Max.
_____
HACK = "H" effective time after CLKIN
_____
HACK = "L" delay time after CLKIN
_____
HACK = "L" effective time after CLKIN
_____
HACK = "H" delay time after CLKIN
Address output disable time after CLKIN
Address output enable time after CLKIN
Data output enable time after CLKIN
Data output delay time after CLKIN
Data output disable time after CLKIN
Data output effective time after CLKIN
__
DC output enable time after CS
__
DC = "H" effective time after CLKIN
__
DC = "L" delay time after CLKIN
__
DC output disable time after CLKIN
__
DC = "L" effective time after CLKIN
Parameter
8
16
15
16
12
Min.
0
ns
Unit
Reference
number
(4) Standby timing
Limits
Symbol
Test conditions
td(CLKIN-STBYHX)
td(CLKIN-STBYL)
td(CLKIN-STBYLX)
td(CLKIN-STBYH)
Reference
number
65
66
67
68
Min.
Unit
Max.
Parameter
ns
tc(CLKIN)n/4+15
_____
STBY = "H" effective time after CLKIN
_____
STBY = "L" delay time after CLKIN (see note)
_____
STBY = "L" effective time after CLKIN
_____
STBY = "H" delay time after CLKIN (see note)
0
_____
Note: The STBY signal is synchronized with the internal clock, therefore its timing changes at 0, 90, 180 and 270 (n=0, 1, 2, 3) degree phase
of CLKIN.
Limits
Symbol
Parameter
Min.
Port output "L" pulse width (see note)
Port output "H" pulse width (see note)
Test conditions
(5) I/O port timing
tw(PORTOUTL)
tw(PORTOUTH)
Max.
Unit
ns
Reference
number
10
71
72
Note: The minimum pulse width value is that where the output is changed within 1 clock of the internal clock. Software processing time to write
to the port data register is not included.
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