參數(shù)資料
型號(hào)： M32000D4BFP-80
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 80 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 35/44頁
文件大?。?/td> 448K
代理商： M32000D4BFP-80
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
40
Fig. 40 Read/write timing
CLKIN
(input)
(output)
0.5 VCC
(input)
(output)
D0 to D15
(input)
td(CLKIN-DV)
td(CLKIN-DZX)
td(CLKIN-DVX)
td(CLKIN-DXZ)
tsu(DCL-CLKIN)
th(CLKIN-DCL)
tsu(D-CLKIN)
th(CLKIN-D)
BS
BCH, BCL
DC
13
15
30
31
32
33
34
35
38
39
(output)
A8 to A30
td(CLKIN-AV)
16
(output)
td(CLKIN-STV)
SID, ST
22
(output)
td(CLKIN-RWV)
R/W
24
(output)
BURST
td(CLKIN-BSH)
td(CLKIN-BURSTL)
27
td(CLKIN-BURSTH)
29
td(CLKIN-BSL)
td(CLKIN-BCV)
18
td(CLKIN-SIDV)
20
12 td(CLKIN-BSHX)
14 td(CLKIN-BSLX)
td(CLKIN-AX)
17
td(CLKIN-BCX)
19
td(CLKIN-STX)
23
td(CLKIN-SIDX)
21
td(CLKIN-RWX)
25
td(CLKIN-BURSTHX)
26
td(CLKIN-BURSTLX)
28
tsu(DCH-CLKIN)
th(CLKIN-DCH)
36
37
*1 The set up/hold of DC = "H" may vary depending on the wait cycle insertion.
*1
*2 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to
the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of
the actual CLKIN is necessary.
minimum value of td(CLKIN-BSLX) = (value in table) – (correction value) = 12.5 – (50 x 5/100) = 10 [ns]
maximum value of td(CLKIN-BSH) = (value in table) + (correction value) = (50/4 + 8) + (50 x 5/100) = 23 [ns]
*2
[example]
BS signal transition ("L" –> "H") when inputting 20MHz clock whose duty ratio is 45 - 55% (± 5%) to CLKIN:
0.5 VCC
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