參數(shù)資料
型號: M30LW128D
廠商: 意法半導(dǎo)體
英文描述: 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product
中文描述: 128兆位(兩個64兆比特,x8/x16,統(tǒng)一座,快閃記憶體)3V電源,多記憶體產(chǎn)品
文件頁數(shù): 34/57頁
文件大?。?/td> 860K
代理商: M30LW128D
M30LW128D
34/57
Figure 14. Write AC Waveforms, Chip Enable Controlled
Note: 1. Refer to Table 3 for details of how the device is enabled.
2. Not available with the LFBGA88 package.
Table 19. Write AC Characteristics, Chip Enable Controlled.
Symbol
Parameter
Test Condition
M30LW128D
Unit
110
t
AVEH
Address Valid to Chip Enable High
W = V
IL
Min
50
ns
t
DVEH
Data Input Valid to Chip Enable High
W = V
IL
Min
50
ns
t
WLEL
Write Enable Low to Chip Enable Low
Min
0
ns
t
VPHEH
Program/Erase Enable High to Chip Enable High
Min
0
ns
t
EHAX
Chip Enable High to Address Transition
W = V
IL
Min
5
ns
t
EHBL
Chip Enable High to Status/(Ready/Busy) low
Max
500
ns
t
EHDX
Chip Enable High to Input Transition
W = V
IL
Min
5
ns
t
EHWH
Chip Enable High to Write Enable High
Min
0
ns
t
GHEL
Output Enable High to Chip Enable Low
Min
20
ns
t
EHGL
Chip Enable High to Output Enable Low
Min
35
ns
t
EHEL
Chip Enable High to Chip Enable Low
Min
30
ns
t
ELEH
Chip Enable Low to Chip Enable High
W = V
IL
Min
70
ns
AI07512
DQ0-DQ15
STS(2)
E
(1)
A0-A23
W
G
INPUT
VALID
tEHWH
tAVEH
tELEH
tWLEL
VPEN
tEHAX
tEHEL
tEHDX
tDVEH
tVPHEH
tEHGL
tGHEL
tEHBL
(Ready/Busy mode)
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