參數(shù)資料
型號(hào): M30L0R8000T0
廠商: 意法半導(dǎo)體
英文描述: 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
中文描述: 256兆位(16Mb的x16插槽,多銀行,多層次,多突發(fā))1.8V電源快閃記憶體
文件頁數(shù): 68/83頁
文件大?。?/td> 1363K
代理商: M30L0R8000T0
M30L0R8000T0, M30L0R8000B0
68/83
Note: 1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Tables
30
,
31
,
32
,
33
,
34
and
35
in
APPENDIX A.
(P+3F)h = 149h
03h
(P+47)h = 151h
03h
Bank Region 2 (Erase Block Type 1):Page mode and
Synchronous mode capabilities (defined in
Table 42.
)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+40)h = 14Ah
03h
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks in
each bank
Bits 16-31: n×256 = number of bytes in erase block region
(P+41)h = 14Bh
00h
(P+42)h = 14Ch
80h
(P+43)h = 14Dh
00h
(P+44)h =14Eh
64h
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
(P+45)h = 14Fh
00h
(P+46)h = 150h
02h
Bank Region 2 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+47)h = 151h
03h
Bank Region 2 (Erase Block Type 2): Page mode and
Synchronous mode capabilities (defined in
Table 42.
)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+48)h = 152h
(P+48)h = 152h
Feature Space definitions
(P+49)h = 153h
(P+43)h = 153h
Reserved
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
Offset
Data
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