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參數(shù)資料
| 型號： | M30L0R8000T0 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| 中文描述： | 256兆位（16Mb的x16插槽，多銀行，多層次，多突發(fā)）1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 11/83頁 |
| 文件大?。?/td> | 1363K |
| 代理商： | M30L0R8000T0 |
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11/83
M30L0R8000T0, M30L0R8000B0
SIGNAL DESCRIPTIONS
See
Figure 2., Logic Diagram
and
Table 1., Signal
Names
, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A23).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Input/Output (DQ0-DQ15).
The Data I/O
output the data stored at the selected address dur-
ing a Bus Read operation or input a command or
the data to be programmed during a Bus Write op-
eration.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at V
IL
and
Reset is at V
IH
the device is in active
mode. When Chip Enable is at V
IH
the memory is
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G).
The Output Enable input
controls data outputs during the Bus Read opera-
tion of the memory.
Write Enable (W).
The Write Enable input con-
trols the Bus Write operation of the memory’s
Command Interface. The data and address inputs
are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
Write Protect (WP).
Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at V
IL
, the Lock-
Down is enabled and the protection status of the
Locked-Down blocks cannot be changed. When
Write Protect is at V
IH
, the Lock-Down is disabled
and the Locked-Down blocks can be locked or un-
locked. (refer to
Table 16., Lock Status
).
Reset (RP).
The Reset input provides a hard-
ware reset of the memory. When Reset is at V
IL
,
the memory is in reset mode: the outputs are high
impedance and the current consumption is re-
duced to the Reset Supply Current I
DD2
. Refer to
Table 21., DC Characteristics - Currents
, for the
value of I
DD2.
After Reset all blocks are in the
Locked state and the Configuration Register is re-
set. When Reset is at V
IH
, the device is in normal
operation. Exiting reset mode the device enters
asynchronous read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
RPH
(refer to
Table 22., DC Characteristics - Voltages
).
Latch Enable (L).
Latch Enable latches the ad-
dress bits on its rising edge. The address
latch is transparent when Latch Enable is at
V
IL
and it is inhibited when Latch Enable is at
V
IH
. Latch Enable can be kept Low (also at
board level) when the Latch Enable function
is not required or supported.
Clock (K).
The clock input synchronizes the
memory to the microcontroller during synchronous
read operations; the address is latched on a Clock
edge (rising or falling, according to the configura-
tion settings) when Latch Enable is at V
IL
. Clock is
ignored during asynchronous read and in write op-
erations.
Wait (WAIT).
Wait is an output signal used during
synchronous read to indicate whether the data on
the output bus are valid. This output is high imped-
ance when Chip Enable is at V
IH
, Output Enable is
at V
IH
, or Reset is at V
IL
. It can be configured to be
active during the wait cycle or one data cycle in ad-
vance.
V
DD
Supply Voltage .
V
DD
provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
DDQ
Supply Voltage.
V
DDQ
provides the power
supply to the I/O pins and enables all Outputs to
be powered independently of V
DD
. V
DDQ
can be
tied to V
DD
or can use a separate supply.
V
PP
Program Supply Voltage.
V
PP
is both a
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin.
If V
PP
is kept in a low voltage range (0V to V
DDQ
)
V
PP
is seen as a control input. In this case a volt-
age lower than V
PPLK
gives an absolute protection
against program or erase, while if V
PP
is within the
V
PP1
range these functions are enabled (see Ta-
bles
21
and
22
, DC Characteristics for the relevant
values). V
PP
is only sampled at the beginning of a
program or erase; a change in its value after the
operation has started does not have any effect and
program or erase operations continue.
If V
PP
is in the range of V
PPH
it acts as a power
supply pin. In this condition V
PP
must be stable un-
til the Program/Erase algorithm is completed.
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