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參數(shù)資料
| 型號： | M30L0R7000B0ZAQE |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| 中文描述： | 128兆位（8兆x16插槽，多銀行，多層次，多突發(fā)），1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 48/83頁 |
| 文件大小： | 1329K |
| 代理商： | M30L0R7000B0ZAQE |
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M30L0R7000T0, M30L0R7000B0
48/83
Table 23. Write AC Characteristics, Write Enable Controlled
Note: 1. Sampled only, not 100% tested.
2. t
WHEL
has the values shown when reading in the targeted bank. System designers should take this into account and may insert a
software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a
different bank t
WHEL
is 0ns.
3. Meaningful only if L is always kept low.
Symbol
Alt
Parameter
M30L0R7000T0/B0
Unit
85
W
t
AVAV
t
WC
Address Valid to Next Address Valid
Min
85
ns
t
AVLH
Address Valid to Latch Enable High
Min
7
ns
t
AVWH(3)
Address Valid to Write Enable High
Min
50
ns
t
DVWH
t
DS
Data Valid to Write Enable High
Min
50
ns
t
ELLH
Chip Enable Low to Latch Enable High
Min
10
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable Low
Min
0
ns
t
ELQV
Chip Enable Low to Output Valid
Min
85
ns
t
ELKV
Chip Enable Low to Clock Valid
Min
9
ns
t
GHWL
Output Enable High to Write Enable Low
Min
17
ns
t
LHAX
Latch Enable High to Address Transition
Min
9
ns
t
LLLH
Latch Enable Pulse Width
Min
9
ns
t
WHAV(3)
Write Enable High to Address Valid
Min
0
ns
t
WHAX(3)
t
AH
Write Enable High to Address Transition
Min
0
ns
t
WHDX
t
DH
Write Enable High to Input Transition
Min
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable High
Min
0
ns
t
WHEL(2)
Write Enable High to Chip Enable Low
Min
25
ns
t
WHGL
Write Enable High to Output Enable Low
Min
0
ns
t
WHLL
Write Enable High to Latch Enable Low
Min
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable Low
Min
25
ns
t
WHQV
Write Enable High to Output Valid
Min
110
ns
t
WLWH
t
WP
Write Enable Low to Write Enable High
Min
50
ns
P
t
QVVPL
Output (Status Register) Valid to V
PP
Low
Min
0
ns
t
QVWPL
Output (Status Register) Valid to Write Protect Low
Min
0
ns
t
VPHWH
t
VPS
V
PP
High to Write Enable High
Min
200
ns
t
WHVPL
Write Enable High to V
PP
Low
Min
200
ns
t
WHWPL
Write Enable High to Write Protect Low
Min
200
ns
t
WPHWH
Write Protect High to Write Enable High
Min
200
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30L0R7000B0ZAQF | 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0ZAQE | AB 35C 7#12,28#16 PIN RECP |
| M30L0R7000T0ZAQF | CAP 0.1UF 50V 10% X7R DIP-2 BULK R-MIL-C-39014 |
| M30L0R7000T0ZAQT | CAP 0.22UF 50V 20% X7R DIP-2 BULK R-MIL-C-39014 |
| M30L0R7000B0ZAQT | CAP 0.047UF 100V 20% X7R DIP-2 BULK R-MIL-C-39014 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30L0R7000B0ZAQF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000B0ZAQT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0ZAQ | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0ZAQE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
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