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參數(shù)資料
| 型號： | M30L0R7000B0ZAQE |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| 中文描述： | 128兆位（8兆x16插槽，多銀行，多層次，多突發(fā)），1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 26/83頁 |
| 文件大小： | 1329K |
| 代理商： | M30L0R7000B0ZAQE |
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M30L0R7000T0, M30L0R7000B0
26/83
See
Table 11., Burst Type Definition
, for the se-
quence of addresses output from a given starting
address in sequential mode.
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to config-
ure the active edge of the Clock, K, during syn-
chronous read operations. When the Valid Clock
Edge bit is Low (set to ’0’) the falling edge of the
Clock is the active edge. When the Valid Clock
Edge bit is High (set to ’1’) the rising edge of the
Clock is the active edge.
Wrap Burst Bit (CR3)
The Wrap Burst bit, CR3, is used to select be-
tween wrap and no wrap. Synchronous burst
reads can be confined inside the 4, 8 or 16 Word
boundary (wrap) or overcome the boundary (no
wrap).
When the Wrap Burst bit is Low (set to ‘0’) the
burst read wraps. When it is High (set to ‘1’) the
burst read does not wrap.
Burst length Bits (CR2-CR0)
The Burst Length bits are used to set the number
of Words to be output during a Synchronous Burst
Read operation as result of a single address latch
cycle.
They can be set for 4 Words, 8 Words, 16 Words
or continuous burst, where all the Words are read
sequentially. In continuous burst mode the burst
sequence can cross bank boundaries.
In continuous burst mode, in 4, 8 or 16 Words no-
wrap, depending on the starting address, the de-
vice asserts the WAIT signal to indicate that a de-
lay is necessary before the data is output.
If the starting address is aligned to a 4 Word
boundary no wait states are needed and the WAIT
output is not asserted.
If the starting address is shifted by 1, 2 or 3 posi-
tions from the four word boundary, WAIT will be
asserted for 1, 2 or 3 clock cycles when the burst
sequence crosses the first 16 Word boundary, to
indicate that the device needs an internal delay to
read the successive Words in the array. WAIT will
be asserted only once during a continuous burst
access. See also
Table 11., Burst Type Definition
.
CR14, CR5
and
CR4
are reserved for future use.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30L0R7000B0ZAQF | 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0ZAQE | AB 35C 7#12,28#16 PIN RECP |
| M30L0R7000T0ZAQF | CAP 0.1UF 50V 10% X7R DIP-2 BULK R-MIL-C-39014 |
| M30L0R7000T0ZAQT | CAP 0.22UF 50V 20% X7R DIP-2 BULK R-MIL-C-39014 |
| M30L0R7000B0ZAQT | CAP 0.047UF 100V 20% X7R DIP-2 BULK R-MIL-C-39014 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30L0R7000B0ZAQF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000B0ZAQT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0ZAQ | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
| M30L0R7000T0ZAQE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory |
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