參數(shù)資料
型號(hào)： M30L0R7000B0ZAQE
廠商： 意法半導(dǎo)體
英文描述： 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
中文描述： 128兆位（8兆x16插槽，多銀行，多層次，多突發(fā)），1.8V電源快閃記憶體
文件頁(yè)數(shù)： 15/83頁(yè)
文件大?。?/td> 1329K
代理商： M30L0R7000B0ZAQE
15/83
M30L0R7000T0, M30L0R7000B0
■
The address must remain the Start Address
throughout programming.
Dual operations are not supported during the Buff-
er Enhanced Factory Program operation and the
command cannot be suspended.
The Buffer Enhanced Factory Program Command
consists of three phases: the Setup Phase, the
Program and Verify Phase, and the Exit Phase,
Please refer to Table 7. Factory Program Com-
mands for detail information.
Refer to
Table 6., Factory Program Command
,
and
Figure 29., Buffer Enhanced Factory Program
Flowchart and Pseudo Code
.
Setup Phase.
The Buffer Enhanced Factory Pro-
gram command requires two Bus Write cycles to
initiate the command.
The first Bus Write cycle sets up the Buffer
Enhanced Factory Program command.
The second Bus Write cycle confirms the
command.
After the confirm command is issued, read opera-
tions output the contents of the Status Register.
The read Status Register command must not be
issued as it will be interpreted as data to program.
The Status Register P/E.C. Bit SR7 should be
read to check that the P/E.C. is ready to proceed
to the next phase.
If an error is detected, SR4 goes high (set to ‘1’)
and the Buffer Enhanced Factory Program opera-
tion is terminated. See Status Register section for
details on the error.
Program and Verify Phase.
The Program and
Verify Phase requires 32 cycles to program the 32
Words to the Write Buffer. The data is stored se-
quentially, starting at the first address of the Write
Buffer, until the Write Buffer is full (32 Words). To
program less than 32 Words, the remaining Words
should be programmed with FFFFh.
Three successive steps are required to issue and
execute the Program and Verify Phase of the com-
mand.
1.
Use one Bus Write operation to latch the Start
Address and the first Word to be programmed.
The Status Register Bank Write Status bit SR0
should be read to check that the P/E.C. is
ready for the next Word.
2.
Each subsequent Word to be programmed is
latched with a new Bus Write operation. The
address must remain the Start Address as the
P/E.C. increments the address location.If any
address that is not in the same block as the
Start Address is given, the Program and Verify
Phase terminates. Status Register bit SR0
should be read between each Bus Write cycle
to check that the P/E.C. is ready for the next
Word.
■
■
3.
Once the Write Buffer is full, the data is pro-
grammed sequentially to the memory array.
After the program operation the device auto-
matically verifies the data and reprograms if
necessary.
The Program and Verify phase can be repeated,
without re-issuing the command, to program addi-
tional 32 Word locations as long as the address re-
mains in the same block.
4.
Finally, after all Words, or the entire block
have been programmed, write one Bus Write
operation to any address outside the block
containing the Start Address, to terminate
Program and Verify Phase.
Status Register bit SR0 must be checked to deter-
mine whether the program operation is finished.
The Status Register may be checked for errors at
any time but it must be checked after the entire
block has been programmed.
Exit Phase.
Status Register P/E.C. bit SR7 set to
‘1’ indicates that the device has exited the Buffer
Enhanced Factory Program operation and re-
turned to Read Status Register mode. A full Status
Register check should be done to ensure that the
block has been successfully programmed. See the
section on the Status Register for more details.
For optimum performance the Buffer Enhanced
Factory Program command should be limited to a
maximum of 100 program/erase cycles per block.
If this limit is exceeded the internal algorithm will
continue to work properly but some degradation in
performance is possible. Typical program times
are given in
Table 15.
.
See
APPENDIX C.
,
Figure 29., Buffer Enhanced
Factory Program Flowchart and Pseudo Code
, for
a suggested flowchart on using the Buffer En-
hanced Factory Program command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Block Erase operation. The
command can be addressed to any bank.
The Program/Erase Resume command is re-
quired to restart the suspended operation.
One bus write cycle is required to issue the Pro-
gram/Erase Suspend command. Once the Pro-
gram/Erase Controller has paused bits SR7, SR6
and/ or SR2 of the Status Register will be set to ‘1’.
The following commands are accepted during Pro-
gram/Erase Suspend:
–
Program/Erase Resume
–
Read Array (data from erase-suspended
block or program-suspended Word is not
valid)
–
Read Status Register
–
Read Electronic Signature
相關(guān)PDF資料
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M30L0R7000B0ZAQF 128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
M30L0R7000T0ZAQE AB 35C 7#12,28#16 PIN RECP
M30L0R7000T0ZAQF CAP 0.1UF 50V 10% X7R DIP-2 BULK R-MIL-C-39014
M30L0R7000T0ZAQT CAP 0.22UF 50V 20% X7R DIP-2 BULK R-MIL-C-39014
M30L0R7000B0ZAQT CAP 0.047UF 100V 20% X7R DIP-2 BULK R-MIL-C-39014
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30L0R7000B0ZAQF 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
M30L0R7000B0ZAQT 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
M30L0R7000T0 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
M30L0R7000T0ZAQ 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
M30L0R7000T0ZAQE 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
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