![](http://datasheet.mmic.net.cn/120000/M308B8SGP_datasheet_3558617/M308B8SGP_12.png)
M32C/8B Group
1. Overview
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 12 of 67
Figure 1.4
Pin Assignment for 100-pin Package
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M32C/8B Group
PLQP0100KB-A
(100P6Q-A)
(top view)
<VCC2>
<VCC1>
P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2 (1)
50
49
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47
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44
43
42
41
40
39
38
37
36
35
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26
27
28
29
30
D8 / P1_0
D7 / AN0_7 / P0_7
D6 / AN0_6 / P0_6
D5 / AN0_5 / P0_5
D4 / AN0_4 / P0_4
D3 / AN0_3 / P0_3
D2 / AN0_2 / P0_2
D1 / AN0_1 / P0_1
D0 / AN0_0 / P0_0
AN_7 / KI3 / P10_7
AN_6 / KI2 / P10_6
AN_5 / KI1 / P10_5
AN_4 / KI0 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AN_0 / P10_0
AVSS
AVCC
VREF
ADTRG / STXD4 / SCL4 / RXD4 / P9_7
D9 / P1_1
D10 / P1_2
ANEX1 / TXD4 / SDA4 / SRXD4 / P9_6
ANEX0 / CLK4 / P9_5
P6_0 /CTS0 / RTS0 /SS0
P5_7 / RDY
P5_6 / ALE
P5_5 / HOLD
P5_4 / HLDA / ALE
P5_3 / CLKOUT / BCLK / ALE
P5_2 / RD
P5_1 / WRH / BHE
P5_0 / WRL / WR
P4_7 / CS0 / A23
P4_6 / CS1 / A22
P4_5 / CS2 / A21
P4_4 / CS3 / A20
P4_3 / A19
P4_2 / A18
P6_7 / TXD1 / SDA1 / SRXD1
P6_6 / RXD1 / SCL1 / STXD1
P7_2 / TA1OUT / V / CLK2
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 (1)
P6_4 /CTS1 / RTS1 /SS1
P6_3 / TXD0 / SDA0 / SRXD0
P6_2 / RXD0 / SCL0 / STXD0
P6_1 / CLK0
P6_5 / CLK1
P4
_1
/
A
1
7
P4
_0
/
A
1
6
P
3
_
7
/
A1
5
,
[A1
5
/
D
1
5
]
P
3
_
6
/
A1
4
,
[A1
4
/
D
1
4
]
P
3
_
5
/
A1
3
,
[A1
3
/
D
1
3
]
P
3
_
4
/
A1
2
,
[A1
2
/
D
1
2
]
P
3
_
3
/
A1
1
,
[A1
1
/
D
1
]
P
3
_
2
/
A1
0
,
[A1
0
/
D
1
0
]
P
3
_
1
/
A
9
,[
A
9
/
D
9
]
P
3
_
0
/
A
8
,[
A
8
/
D
8
]
P
2
_
7
/
A
N
2
_
7
/A
7
,
[A
7
/
D
7
]
P
2
_
6
/
A
N
2
_
6
/A
6
,
[A
6
/
D
6
]
P
2
_
5
/
A
N
2
_
5
/A
5
,
[A
5
/
D
5
]
P
2
_
4
/
A
N
2
_
4
/A
4
,
[A
4
/
D
4
]
VS
S
VC
C
2
P
2
_
3
/
A
N
2
_
3
/A
3
,
[A
3
/
D
3
]
P
2
_
2
/
A
N
2
_
2
/
A
2
,
[
A
2
/
D
2
]
P
2
_
1
/
A
N
2
_
1
/
A
1
,
[
A
1
/
D
1
]
P
2
_
0
/
A
N
2
_
0
/
A
0
,
[
A
0
/
D
0
]
P
1
_
3
/
D
1
P
1
_
4
/
D
1
2
P
1
_
5
/
IN
T
3
/
D
1
3
P
1
_
6
/
IN
T
4
/
D
1
4
P
1
_
7
/
IN
T
5
/
D
1
5
D
A
1
/
S
4
/
R
T
S
4
/
C
T
S
4
/
T
B
4
IN
/
P
9
_
4
D
A
0
/
S
3
/
R
T
S
3
/
C
T
S
3
/
T
B
3
IN
/
P
9
_
3
S
R
X
D
3
/
S
D
A
3
/
T
X
D
3
/
T
B
2
IN
/
P
9
_
2
S
T
X
D
3
/
S
C
L
3
/
R
X
D
3
/
T
B
1
IN
/
P
9
_
1
C
L
K
3
/
T
B
0
IN
/
P
9
_
0
B
Y
T
E
C
N
V
S
X
C
IN
/
P
8
_
7
X
C
O
U
T
/
P
8
_
6
R
E
S
E
T
X
O
U
T
V
S
X
IN
V
C
1
N
M
I
/
P
8
_
5
IN
T
2
/
P
8
_
4
IN
T
1
/
P
8
_
3
IN
T
0
/
P
8
_
2
U
/
T
A
4
IN
/
P
8
_
1
U
/
T
A
4
O
U
T
/
P
8
_
0
T
A
3
IN
/
P
7
_
7
T
A
3
O
U
T
/
P
7
_
6
W
/
T
A
2
IN
/
P
7
_
5
W
/
T
A
2
O
U
T
/
P
7
_
4
S
2
/
R
T
S
2
/
C
T
S
2
/
V
/
T
A
1
IN
/
P
7
_
3
NOTES:
1. P7_0 and P7_1 are N-channel open drain output ports.
2. Refer to Package Dimensions for the pin1 position on the package.
3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
( note 3 )
( note 2 )