參數(shù)資料
型號(hào)： M30825MW-XXXGP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁(yè)數(shù)： 38/48頁(yè)
文件大小： 847K
代理商： M30825MW-XXXGP
30024711
FIGURE 17. Typical Temperature Sensor Application
2.8 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. A single ground plane
should be used, instead of splitting the ground plane into ana-
log and digital areas.
Since digital switching transients are composed largely of
high frequency components, the skin effect tells us that total
ground plane copper weight will have little effect upon the
logic-generated noise. Total surface area is more important
than is total ground plane volume. Coupling between the typ-
ically noisy digital circuitry and the sensitive analog circuitry
can lead to poor performance that may seem impossible to
isolate and remedy. The solution is to keep the analog cir-
cuitry well separated from the digital circuitry.
High power digital components should not be located on or
near any linear component or power supply trace or plane that
services analog or mixed signal components as the resulting
common return current path could cause fluctuation in the
analog input “ground” return of the ADC, causing excessive
noise in the conversion result.
Generally, we assume that analog and digital lines should
cross each other at 90° to avoid getting digital noise into the
analog path. In high frequency systems, however, avoid
crossing analog and digital lines altogether. The input clock
lines should be isolated from ALL other lines, analog AND
digital. The generally accepted 90° crossing should be avoid-
ed as even a little coupling can cause problems at high
frequencies. Best performance at high frequencies is ob-
tained with a straight signal path.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. This is
especially important with the low level drive required of the
ADC08D1520. Any external component (e.g., a filter capaci-
tor) connected between the converter's input and ground
should be connected to a very clean point in the analog
ground plane. All analog circuitry (input amplifiers, filters, etc.)
should be separated from any digital components.
2.9 DYNAMIC PERFORMANCE
The ADC08D1520 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications and avoid
jitter-induced noise, the clock source driving the CLK input
must exhibit low rms jitter. The allowable jitter is a function of
the input frequency and the input signal level, as described in
It is good practice to keep the ADC input clock line as short
as possible, to keep it well away from any other signals and
to treat it as a transmission line. Other signals can introduce
jitter into the input clock signal. The clock signal can also in-
troduce noise into the analog path if not isolated from that
path.
Best dynamic performance is obtained when the exposed pad
at the back of the package has a good connection to ground.
This is because this path from the die to ground is a lower
impedance than offered by the package pins.
2.10 USING THE SERIAL INTERFACE
The ADC08D1520 may be operated in the Non-Extended
Control (non-Serial Interface) Mode or in the extended control
mode. Table 10 and Table 11 describe the functions of pins
3, 4, 14 and 127 in the Non-Extended Control Mode and the
Extended Control Mode, respectively.
2.10.1 Non-Extended Control Mode Operation
Non-extended Control Mode operation means that the Serial
Interface is not active and all controllable functions are con-
trolled with various pin settings. Pin 41 is the primary control
of the extended control enable function. When pin 41 is logic
high, the device is in the Non-Extended Control Mode. If pin
41 is tied to V
A/2 and pin 52 connected to VA/2 or logic high,
the extended control enable function is controlled by pin 14.
The device has functions which are pin programmable when
in the Non-Extended Control Mode. An example is the full-
scale range is controlled in the Non-Extended Control Mode
by setting pin 14 high or low. Table 10 indicates the pin func-
tions of the ADC08D1520 in the Non-Extended Control Mode.
TABLE 10. Non-Extended Control Mode Operation
(Pin 41 V
A/2 and Pin 52 VA/2 or Logic High)
Pin
Low
High
V
A/2
3
Reduced V
OD
Normal V
OD
n/a
4
OutEdge = Neg
OutEdge = Pos
DDR
127
N/A
DES
14
Reduced V
IN
Normal V
IN
Extended
Control
Mode
Pin 3 can be either high or low in the Non-Extended Control
CONTROL for more information.
Pin 4 can be high or low in the Non-Extended Control Mode.
In the Non-Extended Control Mode, pin 4 high or low defines
the edge at which the output data transitions. See 2.5.3 Out-
put Edge Synchronization for more information. If this pin is
tied to V
A/2, the output clock (DCLK) is a DDR (Double Data
Rate) clock (see 1.1.5.3 Double Data Rate) and the output
edge synchronization is irrelevant since data is clocked out
on both DCLK edges.
When in Normal Mode, Pin 127 must be tied high. If pin 127
is tied to V
A/2, the converter performs dual edge sampling
(DES).
TABLE 11. Extended Control Mode Operation (Pin 41
Logic Low and Pin 52 V
A/2 or Logic High)
Pin
Function
3
SCLK (Serial Clock)
4
SDATA (Serial Data)
127
SCS (Serial Interface Chip Select)
43
www.national.com
ADC08D1520QML
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