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| 型號(hào)： | M30600E8-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 75/139頁(yè) |
| 文件大?。?/td> | 1782K |
| 代理商： | M30600E8-XXXGP |
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Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
40
(1) Interrupt control registers
Peripheral I/O interrupts have their own interrupt control registers. Table 1.18 shows the addresses of the
interrupt control registers. Figure 1.26 shows the configuration of the interrupt control registers.
The interrupt request bit is set by hardware to “0” when an interrupt request is received. The interrupt
request bit can also be set by software to “0”. (Do not set to “1”.)
________ _______
________
INT0, INT1, and INT2 are triggered by the edges of external inputs. The edge polarity is selected using the
polarity select bit. (Other interrupts are described elsewhere.)
An interrupt must first be enabled before it can be used to cancel stop mode.
Interrupt control register
Symbol name
Address
Interrupt control register
Symbol name
Address
DMA0 interrupt control register
DM0IC
004B16 DMA1 interrupt control register
DM1IC
004C16
Key input interrupt control register
KUPIC
004D16 A-D interrupt control register
ADIC
004E16
UART0 transmit interrupt control register
S0TIC
005116 UART0 receive interrupt control register
S0RIC
005216
UART1 transmit interrupt control register
S1TIC
005316 UART1 receive interrupt control register
S1RIC
005416
Timer A0 interrupt control register
TA0IC
005516 Timer A1 interrupt control register
TA1IC
005616
Timer A2 interrupt control register
TA2IC
005716 Timer A3 interrupt control register
TA3IC
005816
Timer A4 interrupt control register
TA4IC
005916 Timer B0 interrupt control register
TB0IC
005A16
Timer B1 interrupt control register
TB1IC
005B16 Timer B2 interrupt control register
TB2IC
005C16
________
INT0 interrupt control register
INT0IC
005D16
________
INT1 interrupt control register
INT1IC
005E16
________
INT2 interrupt control register
INT2IC
005F16
Table 1.18. Addresses in interrupt control register
(2) Interrupt priority
The order of priority when two or more interrupts are generated simultaneously is determined by both
hardware and software.
_______
________
The interrupt priority levels determined by hardware are reset > NMI > DBC > wacthdog timer > peripheral
I/O interrupts > single-step > address matching interrupt.
The interrupt priority levels determined by software are as the interrupt priority levels are set in the inter-
rupt control registers.
Figure 1.27 shows the circuit that judges the interrupt priority level. When two or more interrupts are
generated simultaneously, this circuit selects the interrupt with the highest priority level. However, if the
interrupts have the same priority level, the interrupt is selected according to the priority set in the circuit.
The selected interrupt is accepted only when the priority level is higher than the processor interrupt
priority level (IPL) in the flag register (FLG) and the interrupt enable flag (I flag) is “1”. Note that the reset,
_______
________
NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined in-
struction interrupts are generated regardless of the interrupt enable flag (I flag).
Interrupts
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