參數(shù)資料
型號(hào): M30600E8-XXXGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù): 129/139頁(yè)
文件大?。?/td> 1782K
代理商: M30600E8-XXXGP
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Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
9
Pin Description
Signal name
Function
Pin name
I/O type
I/O port P5
Input/output
Input
Input/output
I/O port P6
I/O port P7
I/O port P8
I/O port P85
I/O port P9
I/O port P10
P50 to P57
P60 to P67
P70 to P77
P80 to P84,
P86,
P87,
P85
P90 to P97
P100 to P107
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by software.
Output
Input
Output
Input
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as UART0 and UART1 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as timer A0–A3 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as Timer B0–B2 input pins, D-A converter output pins, A-D converter’s
extended input pins, or A-D trigger input pins as selected by software.
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as A-D converter input pins. Furthermore, P104–P107 also function as
input pins for the key input interrupt function.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state. BCLK outputs
a clock with the same cycle as the internal clock
.
P80 to P84, P86, and P87 are I/O ports with the same functions as P0.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P86 and P87 can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P86 (XCOUT
pin) and P87 (XCIN pin). P85 is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be canceled using
software. The pull-up cannot be set for this pin.
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