參數(shù)資料
型號： M30600E8-XXXGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 67/139頁
文件大?。?/td> 1782K
代理商： M30600E8-XXXGP
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
33
Figure 1.23 shows the configuration of system clock control registers 0 and 1.
Figure 1.23. Configuration of system clock control registers 0 and 1
Function
System clock control register 0 (Note 1)
Symbol
Address
When reset
CM0
0006 16
48 16
Bit name
Function
Bit symbol
b7
b6
b5
b4 b3
b2
b1
b0
0 0 : I/O port P57
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
CM06
Clock output function
select bit
WAIT peripheral function
clock stop bit
0 : Do not stop f1, f8, f32 in wait mode
1 : Stop f1, f8, f32 in wait mode
XCIN-XCOUT drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
Port XC select bit
0 : I/O port
1 : XCIN-XCOUT generation
Main clock (XIN-XOUT)
stop bit (Note 3) (Note 4)
0 : On
1 : Off
Main clock division select
bit 0 (Note 2)
0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Note 5)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop
mode and operating with X IN, set this bit to “0”. When main clock oscillation is operating by
itself, set system clock select bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input
is acceptable.
Note 5: Set port Xc select bit (CM04) to “1” before writing to this bit. The both bits can not be
written at the same time.
System clock control register 1 (Note 1)
Symbol
Address
When reset
CM1
0007 16
20 16
Bit name
Bit symbol
b7 b6
b5
b4
b3
b2
b1 b0
CM10
All clock stop control bit
0 : Clock on
1 : All clocks off (stop mode)
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shiffing to stop mode.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”,
division mode is fixed at 8.
CM15
XIN-XOUT drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
W
R
W
R
CM16
CM17
Reserved bit
Always set to
“0”
Reserved bit
Always set to
“0”
Main clock division
select bit1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
0
Reserved bit
Always set to
“0”
Reserved bit
Always set to
“0”
0
Clock Generating Circuit
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