
Rev.2.00 Oct 16, 2006
page 323 of 354
REJ09B0340-0200
M30245 Group
3. Controlling Power Applications
Figure 3.8.3. Set-up procedure of controlling power using stop mode (1)
Canceling protect
Protect register [Address 000A16]
PRCR
b7b0
1
Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716)
and frequency synthesizer registers (addresses 03DB16 to 03DF16)
1 : Write-enabled
Main
Initial condition
b7b0
Pull-up control register 2
[Address 03FE16]
PUR2
P100 to P103 pulled high
1
Port P10 direction register
[Address 03F616]
PD0
b7
b0
0
Key scan input port
Processor interrupt priority level (IPL) = 0
Interrupt enable flag (I) =0
Key input interrupt control register
[Address 004116]
KUPIC
Interrupt priority level select bit
Set higher value than the present IPL
b7
b0
1
0
Port P0 direction register
[Address 03E216]
PD0
Key scan output port
b7
b0
1
Setting interrupt except stop mode cancel
I
nterrupt control registerSiRIC(i=0,2,3)[Address 004A16, 004216, 005516]
S13BCNIC[Address 004316]
TAiIC(i=0 to 4)[Address 005416, 004516, 004716, 005716, 005916]
EP0IC[Address 004616]
ADIC[Address 004B16]
DMiIC(i=0 to 3)[Address 004C16, 004E16, 005016, 005216]
SiTIC(i=0 to 3)[Address 005316, 005116, 004F16, 004D16]
SUSPIC[Address 005616]
RSMIC[Address 005816]
RSTIC[Address 005A16]
SOFIC[Address 005B16]
VBDIC[Address 005C16]
USBFIC[Address 005D16]
Interrupt priority level select bit
000 : Interrupt disabled
b7
b0
0
Interrupt priority level select bit
000 : Interrupt disabled
b7
b0
0
INTiIC(i=0 to 2) [Address 005F16, 004416, 005E16]
S1RIC
[Address 004816]
S02BCNIC
[Address 004916]
0
Reserved bit
Must always be set to “0”
Setting operation clock after returning from stop mode
System clock control register 0
CM0 [Address 000616]
XCIN-XCOUT generation
Port XC select bit
b7
b0
System clock select bit
XCIN, XCOUT
As this register becomes setting mentioned above when operating with XCIN
(count source of BCLK is XCIN), the user does not need to set it again.
When operating with XIN, set port Xc select bit to “1” before setting system
clock select bit to “1”. The both bits cannot be set at the same time.
1
(When operating with XCIN after returning)
System clock control register 0
CM0
[Address 000616]
On
Main clock (XIN-XOUT) stop bit
b7
b0
System clock select bit
XIN, XOUT
0
(When operating with XIN after returning)
Port P0 register
[Address 03E016]
P0
b7
b0
0
Key scan data
0
As this register becomes setting mentioned above when
operating with XIN (count source of BCLK is XIN),
the user does not need to set it again.
When operating with XCIN, set main clock (XIN-XOUT) stop bit
to “0” before setting system clock select bit to “0”. The both
bits cannot be set at the same time.
Reserved bit
Must always be set to “0”
0
Reserved bit
Must always be set to “0”
0
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