Rev.2.00 Oct 16, 2006
page 247 of 354
REJ09B0340-0200
M30245 Group
2. DMAC
Source
BCLK
DMAi
request bit
DMA transfer
counter
DMAi
interrupt
request bit
DMAi
enable bit
In the case in which the number of transfer times is set to 2.
RD signal
WR signal
Address bus
Data bus
“1”
Write signal to
software DMAi
request bit
Source
Indeterminate
0016
Dummy cycle
CPU use
(3) Underflow
FF16
CPU use
Source
CPU use
Cleared to “0” when interrupt request is accepted, or cleared by software
CPU use
0016
CPU use
Source
CPU use
Destination
0116
Destination
Dummy cycle
Destination
Dummy cycle
Destination
Dummy cycle
Destination
Dummy cycle
(1) Request signal for a DMA transfer occurs
(2) Data transfer begins
In repeat transfer mode, choose functions from the items shown in Table 2.10.2. Operations of the circled
items are described below. Figure 2.10.7 shows an example of operation and Figure 2.10.8 shows the
set-up procedure.
2.10.3 Operation of DMAC (repeated transfer mode)
Figure 2.10.7. Example of operation of repeated transfer mode
O
Item
Transfer space
Unit of transfer
Set-up
O
Fixed address from an arbitrary 1 M bytes space
Arbitrary 1 M bytes space from a fixed address
Fixed address from fixed address
8 bits
16 bits
Table 2.10.2. Choosed functions
(1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA
transfer request signal.
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
forward-direction address pointer are transferred to the address indicated by the DMAi desti-
nation pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 2 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
(3) Though DMAi transfer counter is underflowed, DMA enable bit is still “1”. The DMA interrupt
request bit changes to “1” simultaneously.
(4) After DMAi transfer counter is underflowed, when the next DMA request is generated, DMA
transfer is repeated from (1).
Operation