
Rev.2.00 Oct 16, 2006
page 281 of 354
REJ09B0340-0200
M30245 Group
2. Power Control
2.16.3 Wait Mode Set-Up
Figure 2.16.6. Example of wait mode set-up
Settings and operation for entering wait mode are described here.
(1) Enables the interrupt used for returning from wait mode.
(2) Sets the interrupt enable flag (I flag) to “1”.
(3) Clears the protection and changes the content of the system clock control register.
(4) Executes the WAIT instruction.
Operation
Wait mode
(3) Canceling protect
b7
b0
Protect register [Address 000A16]
PRCR
1
(4) WAIT instruction
(3) Control of CPU clock
Note 1: When switching the system clock, it is necessary to wait for the oscillation to stabilize.
Note 2: Set the WAIT peripheral function clock stop bit to “0” when the system clock select bit is “1”.
b7
b0
Reserved bit
Must always be set to “0”
WAIT peripheral function clock stop bit (Note 2)
0 : Do not stop f1, f8, f32 in wait mode
1 : Stop f1, f8, f32 in wait mode
Port XC select bit
0 : I/O port
1 : XCIN-XCOUT generation
Main clock (XIN-XOUT) stop bit
0 : On
1 : Off
Main clock division select bit 0
0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit (Note 1, Note 2)
0 : XIN, XOUT
1 : XCIN, XCOUT
System clock control register 0
[Address 000616] CM0
b7
b0
System clock control register 1
[Address 000716] CM1
0
Reserved bit
Must always be set to “0”
Main clock division select bit
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
(1) Setting interrupt to cancel wait mode
Make sure that the interrupt priority
level of the interrupt which is used
to cancel the wait mode is higher
than the processor interrupt priority
(IPL) of the routine where the
WAIT instruction is executed.
Interrupt priority level select bit
b7
b0
Make sure that the interrupt priority level of the
interrupt which is used to cancel the wait mode is
higher than the processor interrupt priority (IPL) of
the routine where the WAIT instruction is executed.
Interrupt priority level select bit
b7
b0
0
Reserved bit
Must always be set to “0”
(2) Interrupt enable flag (I flag)
“1”
Insert JMP.B instruction before the WAIT instruction and at least four NOPs after the WAIT instruction.
Interrupt control register
KUPIC[Address 004116]
SiRIC(i=0,2,3)[Address 004A16, 004216, 005516]
S13BCNIC[Address 004316]
TAiIC(i=0 to 4)[Address 005416, 004516, 004716, 005716, 005916]
EP0IC[Address 004616]
ADIC[Address 004B16]
SiTIC(i=0 to 3)[Address 005316, 005116, 004F16, 004D16]
SUSPIC[Address 005616]
RSMIC[Address 005816]
SOFIC[Address 005B16]
VBDIC[Address 005C16]
USBFIC[Address 005D16]
INTiIC(i=0 to 2)
[Address 005F16, 004416, 005E16]
S1RIC
[Address 004816]
S02BCNIC
[Address 004916]
Reserved bit
Must always be set to “0”
0
Enables writing to system clock control registers 0 and 1(addresses 000616 and 000716) and
frequency synthesizer registers (addresses 03DB16 to 03DF16)
1 : Write-enabled
Disable the interrupt not to be used for cancelling wait mode.