參數(shù)資料
型號: M30245FCGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數(shù): 99/244頁
文件大?。?/td> 3535K
代理商: M30245FCGP
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CPU Rewrite Mode
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
188
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be read, programmed, or erased under control of the
Central Processing Unit (CPU). Only the user ROM area, shown in Figure 1.140, can be rewritten. The
boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued only
for each block of the user ROM area.
The control program for CPU rewrite mode can be stored in either the user ROM or the boot ROM area.
Because the flash memory cannot be read from the CPU, the rewrite control program must be trans-
ferred to an area other than the internal flash memory before it can be executed.
Overview
In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as
instructed by software commands. Operations are executed from a memory other than the
internal flash memory, such as the internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 02F716) is set to “1”, transition to CPU
rewrite mode occurs and software commands can be accepted. Read and write software com-
mands and data to even-numbered addresses (“0” for address A0) in 16-bit units. For 8-bit mode,
always write 8-bit software commands to even-numbered addresses. Commands are ignored
with odd-numbered addresses. Use software commands to control program and erase opera-
tions. The status register can verify if a program or erase operation has terminated normally or in
error.
Figure 1.141 shows the flash memory control register 0. Figure 1.142 shows a flowchart for
enabling/disabling the CPU rewrite mode. Always follow the operation as indicated in these
flowcharts.
Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory.
During programming and erase operations, it is “0”. Otherwise, it is “1”.
Bit 1 is the CPU rewrite mode select bit. The CPU rewrite mode is entered by setting this bit to “1”
to make software commands accepted. In CPU rewrite mode, the CPU becomes unable to
access the internal flash memory directly so, write bit 1 in an area other than the internal flash
memory. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession when
the NMI pin is “H” level. The bit can be set to “0” by only writing “0”.
Bit 2 is the lock bit disable bit. By setting this bit to “1”, it is possible to disable erase and write
protect (block lock) effected by the lock bit data. The lock bit disable select bit only disables the
lock bit function; it does not change the lock data bit value. However, if an erase operation is
performed when this bit = “1”, the lock bit data that is “0” (locked) is set to “1” (unlocked) after
being erased. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession.
This bit can be controlled only when the CPU rewrite mode select bit = “1”.
Bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory.
This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When
the CPU rewrite mode select bit is “1”, writing “1” to this bit resets the control circuit. To release
the reset, set this bit to “0”.
Bit 5 is the user ROM area select bit that is effective only in boot mode. If this bit is set to “1”, the
accessed area is switched from the boot ROM area to the user ROM area. When the CPU
rewrite mode is used in boot mode, set this bit to “1”. If the microcomputer is booted from the
user ROM area, the user ROM area is always accessed and this bit has no effect. When in boot
mode, the function of this bit is effective regardless of whether the CPU rewrite mode is on or off.
Use a control program that is not running in the internal flash memory to rewrite this bit.
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