
Universal Serial Bus
77
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
EP1-4 OUT (Receive) FIFOs
The CPU reads data from the endpoint’s FIFO Data Register. The read pointer automatically increments by
2 in word accessing mode or by 1 in byte accessing mode after a read. The CPU must only read data from
the FIFO Data Register when the OUT_BUF_STS1 flag of the corresponding EPx OUT CSR is a “1”.
The user can program each OUT endpoint’s buffer size and starting location, and assign a buffer size up to
1024 bytes in units of 64 bytes to an endpoint. If double buffer mode is selected, the effective buffer size is
2 x buffer size specified.
Continuous transfer mode is available for OUT EP1-4 bulk transfers only. When the continuous transfer
mode is enabled, the user is responsible for ensuring that the buffer size is a multiple of the MAXP value.
Also, the user must ensure that the last data set from the host either contains a short packet or is equal to
the buffer size, otherwise there is no interrupt or status that will signify that the last data set was received.
AUTO_CLR function is available for OUT EP1-4.
AUTO_CLR and continuous transfer mode are disabled:
Single Buffer Mode:
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags
from 002 to 112 after it has successfully received a data packet from the host.
The CPU writes “1” to the CLR_OUT_BUF_RDY bit after the data packet has been unloaded from the
buffer by the CPU (updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags from 112 to 002).
Double Buffer Mode:
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags
after it has successfully received a data packet from the host.
If the buffer has only one data packet, the buffer status flags transition from 002 to 102.
If the buffer has two data packets, the buffer status flags transition from 102 to 112.
The CPU writes “1” to the CLR_OUT_BUF_RDY bit after a data packet has been unloaded from the
buffer by the CPU (updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags).
If the buffer has one more data packet in it, the buffer status flags transition from 112 to 102.
If the buffer has no more data packet in it, the buffer status flags transition from 102 to 002.
AUTO_CLR is disabled and continuous transfer mode enabled:
Single Buffer Mode:
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags
from 002 to 112 after it has successfully received from the host a data set equal to the buffer size, or a
short packet.
The CPU writes “1” to the CLR_OUT_BUF_RDY bit after the data set has been unloaded from the buffer
by the CPU (updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags from 112 to 002 ).
Double Buffer Mode:
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags
after it has successfully received a data set equal to its buffer size or a short packet from the host..
If the buffer has only one data set, the buffer status flags transition from 002 to 102 .
If the buffer has two data sets, the buffer status flags transition from 102 to 112 .