參數(shù)資料
型號: M30240S9-XXXFP
廠商: Mitsubishi Electric Corporation
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: 單片16位CMOS微機
文件頁數(shù): 91/142頁
文件大?。?/td> 1637K
代理商: M30240S9-XXXFP
1-91
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
UART0 through UART2
2.23.1 Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.24
and Table 1.25 list the specifications of the clock synchronous serial I/O mode. Figure 1.82 shows the
UARTi transmit/receive mode register.
Note 1: “n” denotes the value 00
16
to FF
16
that is set to the UART bit rate generator.
Note 2: Maximum 5 Mbps.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi
receive interrupt request bit is not set to “1”.
Table 1.24:
Specifications of clock synchronous serial I/O mode (1)
Item
Specification
Transfer data format
Transfer data length: 8 bits
Transfer clock
When internal clock is selected (bit 3 at addresses 03A0
16
, 03A8
16
, 0378
16
= “0”): fi=2(n+1)
(Note 1) fi = f1, f8, f32
When external clock is selected (bit 3 at addresses 03A0
16
, 03A8
16
, 0378
16
= “1”): Input
from CLKi pin (Note 2)
Transmission/reception
control
CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start
condition
To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at addresses 03A5
16
, 03AD
16
, 037D
16
) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 03A5
16
, 03AD
16
, 037D
16
) = “0”
_ When CTS function selected, CTS input level = “L”
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A4
16
, 03AC
16
, 037C
16
) = “0”:
CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A4
16
, 03AC
16
, 037C
16
) = “1”:
CLKi input level = “L”
Reception start
condition
To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at addresses 03A5
16
, 03AD
16
, 037D
16
) = “1”
_ Transmit enable bit (bit 0 at addresses 03A5
16
, 03AD
16
, 037D
16)
= “1”
_ Transmit buffer empty flag (bit 1 at addresses 03A5
16
, 03AD
16
, 037D
16
) = “0”
Furthermore, if external clock is selected, the following requirements must
also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A4
16
, 03AC
16
, 037C
16
) = “0”:
CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A4
16
, 03AC
16
, 037C
16
) = “1”:
CLKi input level = “L”
When transmitting
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B0
16
, bit 4 at
address 037D
16
) = “0”: Interrupts requested when data transfer from UARTi
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B0
16
, bit 4 at
address 037D
16
) = “1”: Interrupts requested when data transmission from
Error detection
Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi receive buffer is read.
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