參數(shù)資料
型號(hào): M30240S9-XXXFP
廠商: Mitsubishi Electric Corporation
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: 單片16位CMOS微機(jī)
文件頁數(shù): 136/142頁
文件大?。?/td> 1637K
代理商: M30240S9-XXXFP
1-136
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Frequency Synthesizer Interface and DC-DC Converter
Enable the USB clock by setting USBC5 (bit 5 of USBC) to a “1”. (If the USB clock and FCU are
enabled before the voltage on Ext Cap is stable, a phantom USB Reset may be detected, or the ac-
tual USB Reset may not be detected.)
Wait at least 4 cycles of
Φ
, then enable the USB FCU by setting USBC7 (bit 7 of USBC) to a “1”.
Enable other blocks as necessary.
Figure 1.119: PLL and DC-DC Converter Set Up Timing after Hardware Reset
5.1.2.1.1 Precautions after Software Reset
A software reset occurs after writing a ‘1’ to bit ‘3’ of the processor mode register 0 (address 0004
16
). During
software reset, the contents of the internal RAM are preserved as well as all USB, DC-DC converter, and PLL
registers. If the PLL is used as the system clock source, it is important to note that after a software reset oc-
curs, any writes to the frequency synthesizer register will cause it to freeze. This can cause erratic device be-
havior. In order to avoid this, it is recommended that the following procedure be used:
Prior to software reset, switch device clock source from ‘fsyn to f(Xin)’. Please see the Frequency Synthe-
sizer specification for more details.
After software reset using firmware, evaluate the condition of the synthesizer control register (FSC register,
address 03DC
16
, bit ‘0’). This bit is not effected by a software reset and can check to see if the PLL is still
enabled. If so, any setup routine that involves writing to the PLL registers should not be called. At this point,
the clock source can be changed back to fsyn.
5.1.2.2 Set up after USB Reset Signaling Detected
A USB Reset is detected by the USB FCU when an SE0 is present on D+/D- for at least 2.5
μ
s. De-
tection of a USB Reset results in bit 5 of USB Interrupt Status Register 2 (USBIS2) being set to a “1”
and the registers within the USB FCU being reset to their default values. Register USBC and the PLL
registers are not affected by a USB Reset. A USB Function Interrupt request is also generated when
the USB Reset is detected.
No modifications to the frequency synthesizer or DC-DC converter configuration should be made in
the USB Function Interrupt routine. However, all USB FCU registers (addresses 300
16
to 33C
16
) must
be reconfigured to their pre-enumeration state.
RESET
FSE
LS
USBC4
USBC5
USBC7
Wait 2
m
s
Wait (C+1)
m
s
Enable PLL
Enable DC-DC converter
Enable USB Clock
Enable USB FCU
Wait at least 4 cycles of
Φ
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