參數(shù)資料
型號(hào): M30240ECFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù): 43/231頁(yè)
文件大?。?/td> 3508K
代理商: M30240ECFP
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118
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specifications REV. G
Specifications in this manual are tentative and subject to change
Precautions
1.3.1.3 Dedicated Input Pins
If a dedicated input pin is connected to a power supply different from the supply that Vcc is connected
to, a resistor (approximately 1k ohm) should be added between the input pin and the connected power
supply. However, if the dedicated input pin voltage is higher than Vcc, latch up could occur.
A resistor is not required when using a Vcc voltage equal or greater than the voltage of the dedicated
input pin.
1.3.1.4 DMAC
DMA enable bit
The DMA enable bit is assigned to bit 3 of the DMA0 and DMA1 control registers. DMA becomes ac-
tive when the DMA enable bit is set to “1”. Immediately after the DMA becomes active, the data trans-
fers start and perform the following operations:
Reloads the value of the source pointer or destination pointer depending on which is specified for the
forward direction address pointer
Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting “1” to the DMA enable bit with the DMAC being inactive carries out the operations
given above, so the DMAC operates again from the initial state at the instant “1” is overwritten to the
DMA enable bit.
DMA request bit
The DMA request bit turns to “1” if the DMA transfer request signal occurs regardless of the DMAC’s
state (regardless of weather the DMA enable bit is set to “1” or to “0”). It turns immediately before data
transfer starts.
In addition, it can be set to “0” by the use of a program, but cannot be set to “1”.
There can be instances in which a change in DMA request factor selection bit causes the DMA request
bit to turn to “1”. So be sure to set the DMA request bit to “0” after the DMA request factor selection bit
is changed.
The DMA request bit turns to “1” if a DMA transfer request signal occurs, and turns to “0” immediately
before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the
DMA request bit, if read by use of a program, turns to be “0” in most cases. To examine whether the
DMAC is active, read the DMA enable bit.
To best judge the state of the DMAC, the DMA enable bit should be read instead of the DMA request
bit.
1.3.1.5 Frequency Synthesizer
Refer to Section 1.5.1.2 for setup procedures required after a hardware reset.
Set the value of the Frequency Synthesizer Prescaler register (FSP) so that fPIN is 1 MHZ or higher.
1.3.1.6 Interrupt
Reading address 0000016
When a maskable interrupts occurs, the CPU reads the interrupt information (the interrupt number
and interrupt request level) in the interrupt sequence.
The interrupt request bit of the corresponding interrupt written in address 0000016 is then set to “0”.
Do not read address 0000016 by software.
Reading address 0000016 by software sets the highest priority enabled interrupt source request bit to “0”
Therefore the interrupt routine may not be executed even though the interrupt is generated.
Setting the stack pointer
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