參數(shù)資料
型號: M30240ECFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 205/231頁
文件大?。?/td> 3508K
代理商: M30240ECFP
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁當前第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁
56
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specifications REV. G
Specifications in this manual are tentative and subject to change
Universal Serial Bus
1.2.18.4.13 USB Endpoint 0 OUT Write Count Register
The USB Endpoint 0 OUT Write Count (WRT CNT) Register, shown in Figure 1.46, contains the number of
bytes of the current data set in the OUT FIFO. The USB FCU sets the value in the Write Count Register after
having successfully received a packet of data from the host. The CPU reads the register to determine the number
of bytes to be read from the FIFO.
Figure 1.46: USB Endpoint 0 OUT WRT CNT
1.2.18.4.14 USB Endpoint x IN Control and Status Register
The USB Endpoint x IN CSR (Control and Status Register), shown in Figure 1.47, contains control and status
information of the respective IN endpoint 1-4.
INxCSR0 (IN_PKT_RDY) and INxCSR5 (TX_FIFO_NOT_EMPTY):
These two bits are for IN FIFO status when in read operation (see “IN (Transmit) FIFO” operation for details).
The CPU writes a “1” to the INxCSR0 bit to inform the USB FCU that a packet of data is written to the FIFO.
The USB FCU updates the pointers up on this bit set. The USB FCU also updates the pointers upon a packet
of data successfully sent to the host. When the pointer updates are completed, the IN FIFO status is shown
on INxCSR0 and INxCSR5 bits for the CPU to read. The CPU must allow at least one wait state between writ-
ing and reading these bits for proper FIFO status.
INxCSR1 (UNDER_RUN):
This bit is used in ISO mode only to indicate to the CPU that a FIFO underrun has occurred. The USB FCU
sets this bit to a “1” at the beginning of an IN token if no data packet is in the FIFO. Setting this bit causes the
INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a “0” to clear this bit.
INxCSR2 (SEND_STALL):
The CPU writes a “1” to this bit when the endpoint is stalled (transmitter halt). The USB FCU returns a STALL
handshake while this bit is set. The CPU writes a “0” to clear this bit.
INxCSR3 (ISO/TOGGLE_INIT):
When the endpoint is used for isochronous data transfer, the CPU sets this bit to a “1” for the entire duration
of the isochronous transfer. With the ISO bit set to a “1”, the device uses DATA0 as the pid for all packets sent
back to the host.
When the endpoint is required to initialize the data toggle, this set/reset of the TOGGLE_INIT bit method as-
sumes that there is no activity IN transaction to the respective endpoint on the bus at the time the initialization
process is ongoing. Set/reset of the TOGGLE_INIT bit is performed only when an endpoint experiences a con-
figuration event.
INxCSR4 (INTPT):
The CPU writes a “1” to this bit to initialize this endpoint as a status change endpoint for IN transactions. This
bit is set only when the corresponding endpoint is to be used to communicate rate feedback information (see
Chapter. IN (Transmit) FIFOs for details).
INxCSR5 (TX_FIFO_NOT_EPT):
The USB FCU sets this bit to a “1” when there is at least one data packet in the IN FIFO. This bit, in conjunction
with IN_PKT_RDY bit, provides the transmit IN FIFO status information (see “IN (Transmit) FIFO” for details).
INxCSR6 (FLUSH):
USB Endpoint 0 OUT Write Count Register
Symbol
Address
When reset
EP0WC
031516
0016
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
W_CNT0 to
W_CNT4
Function
W
R
Receive byte count
Reserved
Must always be set to "0"
X
0 0 0
相關(guān)PDF資料
PDF描述
M30240M5-XXXXFP 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
M30240M6-XXXXFP 16-BIT, OTPROM, MICROCONTROLLER, PQFP80
M30240ECFP 16-BIT, OTPROM, MICROCONTROLLER, PQFP80
M30621FCMGP 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80
M30625FGMGP 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30240EC-XXXFP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30240F1 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30240F1-XXXFP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30240F2 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30240F2-XXXFP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER