- 您現在的位置：買賣IC網 > PDF目錄69009 > M30240ECFP 16-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQFP80 PDF資料下載
參數資料
| 型號： | M30240ECFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數： | 203/231頁 |
| 文件大小： | 3508K |
| 代理商： | M30240ECFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁當前第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁
54
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specifications REV. G
Specifications in this manual are tentative and subject to change
Universal Serial Bus
1.2.18.4.11 USB Endpoint 0 Control and Status Register
The Endpoint 0 CSR (Control and Status Register), shown in Figure 1.44 contains the control and status in-
formation of Endpoint 0.
EP0CSR0 (OUT_PKT_RDY):
The USB FCU sets this bit to a “1” after it receives a valid SETUP/OUT token from the host. The CPU clears this
bit after unloading the packet from the FIFO by writing a “1” to EP0CSR6. The CPU should not clear the
OUT_PKT_RDY bit before it finishes decoding the host request. When EP0CSR2 (SEND_STALL) needs to be
set (because the CPU decodes an invalid or unsupported request) a “1” should be written to EP0CSR6 and
EP0CSR2 at the same time using the same instruction.
EP0CSR1 (IN_PKT_RDY):
The CPU writes a “1” to this bit after it finishes writing a packet of data to the endpoint 0 FIFO. The USB FCU
clears this bit after the packet is successfully transmitted to the host, or the EP0CSR5 (SETUP_END) bit is set.
EP0CSR2 (SEND_STALL):
The CPU writes a “1” to this bit when it decodes an invalid or unsupported standard device request from the
host. When the OUT-PKT_RDY bit is a “1” at the time the CPU wants to set the SEND_STALL bit to a “1”, the
CPU must also set SERVICED_OUT_PKT_RDY to a “1” to clear the OUT-PKT_RDY at the same time as set-
ting the SEND_STALL bit. The USB FCU returns a STALL handshake for all subsequent IN/OUT transactions
(during control transfer data or status stages) while this bit is set. The CPU writes a “0” to clear it after it re-
ceives a new SETUP packet. It is up to the firmware to decide what SETUP packet should lead the clearing
of the SEND_STALL bit.
EP0CSR3 (DATA_END):
The CPU writes a “1” to this bit when it writes (IN data phase) or reads (OUT data phase) the last packet of
data to or from the FIFO. The CPU sets this bit at the same time as it sets the last IN_PKT_RDY bit or sets
the last SERVICED_OUT_PKT_RDY bit.This bit indicates to the USB FCU that the specific amount of data in
the setup phase is transferred. The USB FCU advances to the status phase once this bit is set. When the sta-
tus phase completes, the USB FCU clears this bit. When this bit is set to a “1”, and the host requests or sends
more data, the USB FCU returns a STALL handshake and terminates the current control transfer.
EP0CSR4 (FORCE_STALL):
The USB FCU sets this bit to a “1” to report an error status when one of the following occur:
Host sends an IN token in the absence of a SETUP stage
Host sends a bad data toggle in the STATUS stage, (i.e. DATA0 is used)
Host sends a bad data toggle in the SETUP stage, (i.e. DATA1 is used)
Host request more data than specified in the SETUP state,
(i.e. IN token comes after DATA_END bit is set)
Host sends more data than specified in the SETUP state,
(i.e. OUT token comes after DATA_END bit is set)
Host sends larger data packet than MAXP size
All of the conditions stated (except bad data toggle in the SETUP stage) cause the device to send a STALL
handshake for the current IN/OUT transaction. For the bad data toggle in the SETUP state, the device sends
ACK for the SETUP stage and then sends STALL for the next IN/OUT transaction. A STALL handshake
caused by the above listed conditions lasts for one transaction and terminates the ongoing control transfer.
Any packet after the STALL handshake will be seen as the beginning of a new control transfer.
The CPU writes a “0” to clear the FORCE_STALL status bit.
EP0CSR5 (SETUP_END):
The USB FCU sets this bit to a “1” if a control transfer has ended before the specific length of data is trans-
ferred during the data phase (status phase starts before DATA_END bit is set) or a control transfer has ended
before a new SETUP has arrived and before successfully completing the status phase. The CPU clears this
bit by writing a “1” to IN0CSR7. Once the CPU detects the SETUP_END flag as set, it should stop accessing
the FIFO to service the previous setup transaction. If the SETUP_END is caused by the reception of the SET-
UP packet prior to the end of the current control transfer, the OUT_PKT_RDY bit is set once the reception of
the SETUP packet has completed (without errors). After the OUT_PKT_RDY bit is set, the new SETUP packet
相關PDF資料 |
PDF描述 |
|---|---|
| M30240M5-XXXXFP | 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80 |
| M30240M6-XXXXFP | 16-BIT, OTPROM, MICROCONTROLLER, PQFP80 |
| M30240ECFP | 16-BIT, OTPROM, MICROCONTROLLER, PQFP80 |
| M30621FCMGP | 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80 |
| M30625FGMGP | 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M30240EC-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240F1 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240F1-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240F2 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240F2-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購，3分鐘左右您將得到回復。