參數(shù)資料
型號： M30218MFCFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 99/161頁
文件大?。?/td> 2043K
代理商： M30218MFCFP
42
Under
development
Tentative Specifications REV.A
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC)
for an address match interrupt varies depending on the instruction being executed.
Figure DD-12 shows the address match interrupt-related registers.
Bit name
Bit symbol
SymbolAddress
When reset
AIER000916
XXXXXX002
Address match interrupt enable register
Function
W
R
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
SymbolAddress
When reset
RMAD0001216 to 001016
X0000016
RMAD1001616 to 001416
X0000016
b7b6b5b4b3b2b1b0
W
R
Address setting register for address match interrupt
FunctionValues that can be set
Address match interrupt register i (i = 0, 1)
0000016 to FFFFF16
0 : Interrupt disabled
1 : Interrupt enabled
b0b7b0
b3
(b19)(b16)
b7b0
(b15)(b8)
b7
(b23)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Figure DD-12. Address match interrupt-related registers
Address Match Interrupt
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