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參數(shù)資料
| 型號： | M30218MFCFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 154/161頁 |
| 文件大?。?/td> | 2043K |
| 代理商： | M30218MFCFP |
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Under
development
Tentative Specifications REV.A
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
92
Serial I/O
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table GA-1
lists the specifications of the clock synchronous serial I/O mode. Figure GA-6 shows the UARTi transmit/
receive mode register.
Table GA-1. Specifications of clock synchronous serial I/O mode
Specification
Transfer data length: 8 bits
When internal clock is selected (bit 3 at address 03A016, 03A816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
When external clock is selected (bit 3 at address 03A016, 03A816 =“1”) : Input from CLKi pin (Note 2)
_______
________
_______ ________
CTS function/ RTS function/ CTS,RTS function chosen to be invalid
To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at address 03A516, 03AD16) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
_______
_ When CTS function is selected, CTS input level = "L"
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “1”: CLKi input level = “L”
To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at address 03A516, 03AD16) = “1”
_ Transmit enable bit (bit 0 at address 03A516, 03AD16) = “1”
_ Transmit buffer empty flag (bit 1 at address 03A516, 03AD16) = “0”
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “1”: CLKi input level = “L”
When transmitting
_ Transmit interrupt cause select bit (bits 0,1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register to
UARTi transmit register is completed
_ Transmit interrupt cause select bit (bits 0,1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is completed
When receiving
_ Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi re-
ceive buffer register are read out
CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
Transfer clock output from multiple pins selection
UART1 transfer clock can be set 2 pins, and can be selected to output from
which pin.
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: Maximum 5 Mbps.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
Item
Transfer data format
Transfer clock
Transmission/reception control
Transmission start condi-
tion
Reception start condition
Interrupt request
generation timing
Error detection
Select function
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