56
FLD controller
M
i
t
s
u
M
S
b
i
s
3
M
h
0
I
C
i
m
2
R
i
1
O
c
r
8
C
o
c
o
G
M
m
p
r
P
u
t
u
T
e
r
p
R
s
o
U
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
O
E
Figure 39. FLDC-related Register(1)
FLDC mode register
b7
b6
b5
b4
Symbol
FLDM
Address
0350
16
When reset
00
16
Bit name
Function
Bit symbol
b3
b2
b1
b0
Automatic display
control bit
Display start bit
0 : General-purpose mode
1 : Automatic display mode
0 : Stop display
1 : Display
(start to display by switching “0” to “1”)
b3b2
FLDM0
FLDM1
FLDM2
FLDM3
Tscan control bits
00 : FLD digit interrupt
(at rising edge of each digit)
01 : 1 X Tdisp
10 : 2 X Tdisp
11 : 3 X Tdisp
0 : 16 timing mode
1 : 32 timing mode
Timing number control bit
Gradation display mode
selection control bit
Tdisp counter
count source selection bit
High-breakdown voltage
port drivability select bit
0 : Not selecting
1 : Selecting (Note )
0 : f(X
IN
)/32
1 : f(X
IN
)/128
0 : Drivability strong
1 : Drivability weak
FLDM4
FLDM5
Note :
When a gradation display mode is selected, a number of timing is max. 16 timing.
(Set the timing number control bit to “0”.)
FLD output control register
FLDM6
FLDM7
Symbol
FLDCON
Address
0351
16
When reset
00
16
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3 b2
b1
b0
FLDCON7
FLDCON5
FLDCON4
FLDCON2
FLDCON0
FLDCON6
P4
4
to P4
7
FLD
output reverse bit
P4
4
to P4
7
FLD
Toff is invalid bit
0 : Perform normally
1 : Toff is invalid
P9
7
dimmer output
control bit
CMOS ports: section of
Toff generate/not
generate bit
High-breakdown-voltage ports:
section of Toff
generate/not generate bit
0 : Output normally
1 : Dimmer output
0 : section of Toff does NOT generate
1 : section of Toff generates
0 : section of Toff does NOT generate
1 : section of Toff generates
Toff2
SET/RESET change bit
0 : gradation display data is reset at Toff2
(set at Toff1)
1 : gradation display data is set at Toff2
(reset at Toff1)
W
R
AA
AA
AA
AA
AA
AA
0 : Output normally
1 : Reverse output
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
Tdisp time set register
Symbol
TDISP
Address
0352
16
When reset
00
16
Values that can be set
0
16
to FF
16
b7
b0
Counts Tdisp time. Count source is selected by Tdisp
counter count source select bit.
W
R
AA
AA
Function
FLD blanking
interrupt (at falling
edge of last digit)
W
R
AA
AA
AA
AA
AA
AA
AA
AA
AA