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Power Control
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(2) Switching the driving capacity of the oscillation circuit
Both the main clock and the secondary clock have the ability to switch the driving capacity. Reducing
the driving capacity after the oscillation stabilizes allows for further reduction in power consumption.
(3) Clearing stop mode and wait mode
The stop mode and wait mode can be cleared by generating an interrupt request, or by resetting
hardware. Set the priority level of the interrupt to be used for clearing, higher than the processor
interrupt priority level (IPL), and enable the interrupt enable flag (I flag). When an interrupt clears a
mode, that interrupt is processed. Table 2.14.1 shows the interrupts that can be used for clearing a
stop mode and wait mode.
(4) BCLK in returning from wait mode or stop mode
(a) Returning from wait mode
The processor immediately returns to the BCLK, which was in use before entering wait mode.
(b) Returning from stop mode
CM06 is set to “1” when the device enters stop mode after selecting the main clock for BCLK. CM17,
CM16, and CM07 do not change state. In this case, when restored from stop mode, the device starts
operating in divided-by-8 mode.
When the device enters stop mode after selecting the subclock for BCLK, CM06, CM17, CM16, and
CM07 all do not change state. In this case, when restored from stop mode, the device starts operat-
ing in low-speed mode.
Table 2.14.1. Interrupts available for clearing stop mode and wait mode
Can be used when an external clock in clock synchronous serial I/O mode is selected.
Can be used when the external signal is being counted in event counter mode.
Can be used in one-shot mode and one-shot sweep mode.
Note 1:
Note 2:
Note 3:
CM02 = 0
Impossible
Impossible
Note 3
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Impossible
Impossible
Impossible
Note 1
Note 1
Note 1
Note 1
Impossible
Impossible
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Possible
Possible
Possible
Possible
Possible
Possible
DMA0 interrupt
DMA1 interrupt
A-D interrupt
UART0 transmit interrupt
UART0 receive interrupt
UART1 transmit interrupt
UART1 receive interrupt
SI/O automatic transfer interrupt
FLD interrupt
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer B0 interrupt
Timer B1 interrupt
Timer B2 interrupt
INT0 interrupt
INT1 interrupt
INT2 interrupt
INT3 interrupt
INT4 interrupt
INT5 interrupt
Wait mode
Interrupt for clearing
Stop mode
CM02 = 1
Impossible
Impossible
Impossible
Note 1
Note 1
Note 1
Note 1
Impossible
Impossible
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Possible
Possible
Possible
Possible
Possible
Possible