318
FLD controller
2.7.6 FLD operation (Display with digit expander M35501FP: column discrepancy)
The FLD controller can choose functions from those listed in Table 2.7.4. The circled items are described
in detail below. Figure 2.7.22 shows the connection example and Figure 2.7.23 shows the operation
timing, and Figures 2.7.24 and 2.7.27 show the set-up procedures.
Remarks: Also refer to the M35501FP data sheet on http://www.infomicom.mesc.co.jp
Table 2.7.4. Selectable functions
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Note 1: When selecting the FLD blanking interrupt, any one of 1
Tdisp, 2
Tdisp, or 3
Tdisp can be selected as
Tscan time.
Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number.
Operation (1) The FLD starts an automatic display when both the automatic display control bit and the
display start bit are set to “1”.
(2) The display data, the contents from the first address through the last address, in the FLD
automatic display RAM for each port is output to each port. The last address is the result of
decreasing the number indicated in the FLD data pointer from the first address. The grada-
tion display control data is arranged at an address which is calculated by subtracting “70
16
”
from the stored address in the FLD automatic display RAM of the corresponding timing and
pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”.
(3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF
16
”, the
pointer is reloaded and starts counting over again.
(4) Supply signals to the RESET pin and SEL pin of the M35501FP from ports P7
0
and P7
1
,
respectively. Supply the dimmer signal to the CLK pin from the DIM
OUT
(P9
7
).
(5) Input the OVF
OUT
output of the M35501FP to TB2
IN
(P7
2
) and count the input signals as a
count source with Timer B2. Generate the Timer A0 interrupt at FLD display intervals and
confirm the value of Timer B2. If the value is incorrect, reset the M35501FP.
(6) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to
the display start bit.
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