340
A-D Converter
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s
3
M
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0
I
C
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m
2
R
i
1
O
c
r
8
C
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c
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p
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-
C
H
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P
1
6
-
B
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O
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E
2.8.6 Operation of A-D Converter (in repeat sweep mode 1)
In repeat sweep mode 1, choose functions from those listed in Table 2.8.6. Operations of the circled items are
described below. Figure 2.8.13 shows ANi pin's sweep sequence, Figure 2.8.14 shows timing chart, and Figure
2.8.15 shows the set-up procedure.
Figure 2.8.14. Operation timing of repeat sweep mode 1
Operation
(1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage
input to the AN
0
pin.
(2) After the A-D conversion on voltage input to the AN
0
pin is completed, the content of the successive
comparison register (conversion result) is transmitted to A-D register 0.
(3) Every time the A-D converter carries out A-D conversion on a selected analog input pin, the A-D converter
carries out A-D conversion on only one unselected pin, and then the A-D converter carries out A-D conver-
sion from the AN
0
pin again. (See Figure 2.8.13.) The conversion result is transmitted to A-D register i
every time conversion on a pin is completed. The A-D conversion interrupt request bit does not go to “1”.
(4) The A-D converter continues operating until software goes the A-D convers
ion start flag to “0”.
Table 2.8.6. Choosed functions
Item
Figure 2.8.13. ANi pin's sweep sequence in repeat sweep mode 1
Item
Set-up
Set-up
Operation clock
φ
AD
Divided-by-4 f
AD
/ divided-
by-2 f
AD
/ f
AD
8-bit / 10-bit
O
Resolution
Analog input pin
An
0
(1 pin) / AN
0
and AN
1
(2
pins) / AN
0
to AN
2
(3 pins) /
AN
0
to AN
3
(4 pins)
O
O
Sample & Hold
Not activated
Activated
O
When AN
0
is selected
C
Time
0
0
0
0
0
0
0
0
0
0
.
.
.
1
2
3
4
5
6
7
1
2
When AN
0
, AN
1
are selected
C
Time
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
.
.
.
0
2
C
Time
0
1
0
1
0
1
0
1
0
1
0
1
0
.
.
.
2
2
2
2
2
2
3
4
5
6
7
3
When AN
0
to AN
2
are selected
C
Time
0
1
2
0
1
2
0
1
2
0
1
2
0
1
0
.
.
.
3
3
3
3
2
3
4
5
6
7
4
When AN
0
to AN
3
are selected
A-D
conversion
start flag
“1”
“0”
A-D register 0
A-D register 1
φ
AD
A-D register 2
Result
Result
Result
Set to “1” by software
Result
Cleared to “0” by software
(2)
(3) Consecutive conversion
8-bit resolution :
28
φ
AD
cycles
10-bit resolution :
33
φ
AD
cycles
A-D
conversion
is complete
(4)
Conversion result is
transfered to A-D
conversion register 0
Note: When
φ
AD
frequency is less than 1MHz, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49
φ
AD
cycles for 8-bit resolution and 59
φ
AD
cycles for 10-bit resolution.
8-bit resolution :
28
φ
AD
cycles
10-bit resolution :
33
φ
AD
cycles
8-bit resolution :
28
φ
AD
cycles
10-bit resolution :
33
φ
AD
cycles
8-bit resolution :
28
AD
cycles
10-bit resolution :
33
AD
cycles
(1) Start AN
0
pin conversion