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Clock-Synchronous Serial I/O
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2.4.1 Overview
Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The
following is an overview of the clock-synchronous serial I/O.
(1) Transmission/reception format
8-bit data
(2) Transfer rate
If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit
rate generator division, becomes the transfer rate. The bit rate generator count source can be se-
lected from the following: f
1
, f
8
, and f
32
. Clocks f
1
, f
8
, and f
32
are derived by dividing the CPU’s main
clock by 1, 8, and 32 respectively.
Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK
pin becomes the transfer rate.
(3) Error detection
Only overrun error can be detected. Overrun error is an error that occurs when the next data is made
ready before the reception buffer register is read.
(4) How to deal with an error
When receiving data, read an error flag and reception data simultaneously to determine which error
has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer
register, then receive the data again.
To initialize the UARTi receive buffer register
1. Set the receive enable bit to “0” (disable reception).
2. Set the serial I/O mode select bit to “000
2
” (invalid serial I/O).
3. Set the serial I/O mode select bit.
4. Set the receive enable bit to “1” again (enable reception).
To transmit data again due to an error on the reception side, set the UARTi transmit buffer register
again, then transmit the data again.
To set the UARTi transmit buffer register again
1. Set the serial I/O mode select bits to “000
2
” (invalidate serial I/O).
2. Set the serial I/O mode select bits again.
3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi
transmit buffer register.
(5) Function selection
For clock-synchronous serial I/O, the following functions can be selected:
(a) CTS/RTS function
CTS pin. The CTS pin input level is detected when transmission/reception starts. Therefore, if the
level is set to “H” during transmission/reception, it will stop from the next data.
The RTS function informs an external IC that RTS is reception-ready and has changed to “L”. RTS
goes to “H” at the falling edge of the transfer clock.
The clock-synchronous serial I/O has three types of CTS/RTS functions to choose from:
CTS/RTS functions disabled
CTS/RTS pin is a programmable I/O port.
CTS function only enabled
CTS/RTS pin performs the CTS function.
RTS function only enabled
CTS/RTS pin performs the RTS function.
2.4 Clock-Synchronous Serial I/O