參數(shù)資料
型號: M30201M2
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機
文件頁數(shù): 9/159頁
文件大?。?/td> 2319K
代理商: M30201M2
Unde
Memory
deeopmen
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
9
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
004E
16
004F
16
0050
16
0051
16
0052
16
0053
16
0054
16
0055
16
0056
16
0057
16
0058
16
0059
16
005A
16
005B
16
005C
16
005D
16
005E
16
005F
16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Timer X0 interrupt control register (TX0IC)
Timer X1 interrupt control register (TX1IC)
Timer X2 interrupt control register (TX2IC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
INT1 interrupt control register (INT1IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
INT0 interrupt control register (INT0IC)
Figure 1.7. Location of peripheral unit control registers (1)
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