參數(shù)資料
型號: M30201M2
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機
文件頁數(shù): 86/159頁
文件大?。?/td> 2319K
代理商: M30201M2
Unde
Clock asynchronous serial I/O (UART) mode
deeopmen
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
86
Figure 1.79. UARTi transmit/receive mode register in UART mode
Symbol
UiMR(i=0,1)
Address
03A0
16
, 03A8
16
When reset
00
16
CKDIR
UARTi transmit / receive mode registers
Internal / external clock
select bit (Note)
Stop bit length select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Bit name
Function
Bit symbol
b7 b6
b5
b4
b3
b2
b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Odd / even parity
select bit
Parity enable bit
Sleep select bit
A
A
A
A
A
A
A
A
Note: UART1 can use only internal clock. Must set this bit to “1”.
Table 1.29 lists the functions of the input/output pins during UART mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-
channel open-drain is selected, this pin is in floating state.)
Table 1.29. Input/output pin functions in UART mode
Pin name
Function
TxDi
(P5
0
, P4
0
)
Method of selection
Serial data output
Serial data input
Programmable I/O port
Transfer clock input
RxDi
(P5
1
, P4
2
)
CLK0
(P5
2
)
Internal/external clock select bit (bit 3 at address 03A0
16
) = “0”
Internal/external clock select bit (bit 3 at address 03A0
16
) = “1”
Port P5
1
and P4
2
direction register (bit 1 at address 03EB
16
, bit 2 at
address 03EA
16
)= “0”
(Can be used as an input port when performing transmission only)
Port P5
1
and P4
2
direction register (bit 0 at address 03EB
16
, bit 0 at
address 03EA
16
)= “1”
(Can be used as an input port when performing reception only)
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