參數(shù)資料
型號： M30101M3-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PDSO42
封裝： PLASTIC, SSOP-42
文件頁數(shù)： 77/125頁
文件大?。?/td> 1608K
代理商： M30101M3-XXXFP
Under
development
Tentative Specifications REV.C1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30101/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
55
Bit name
Bit symbol
Symbol
Address
When reset
AIER
000916
XXXXXX002
Address match interrupt enable register
Function
W
R
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
Symbol
Address
When reset
RMAD0
001216 to 001016
X0000016
RMAD1
001616 to 001416
X0000016
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
b7
b6
b5
b4
b3
b2
b1
b0
W
R
Address setting register for address match interrupt
Function
Values that can be set
Address match interrupt register i (i = 0, 1)
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
0 : Interrupt disabled
1 : Interrupt enabled
b0 b7
b0
b3
(b19)
(b16)
b7
b0
(b15)
(b8)
b7
(b23)
Address Match Interrupt
Address Match Interrupt
An address match interrupt is generated immediately before the instruction at the address indicated by the
address match interrupt register is executed. Two address match interrupts can be set, each of which can
be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not
affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the
program counter (PC) for an address match interrupt varies depending on the instruction being executed.
Figure 1.12.15 shows the address match interrupt-related registers.
Figure 1.12.15. Address match interrupt-related registers
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