參數(shù)資料
型號： M2V56S30ATP-7
廠商： Mitsubishi Electric Corporation
英文描述： 256M Synchronous DRAM
中文描述： 256M同步DRAM
文件頁數(shù)： 18/49頁
文件大?。?/td> 244K
代理商： M2V56S30ATP-7
Feb.2000
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
18
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any active bank. Random column access is
allowed. READ to READ interval is minimum 1 CLK.
Read interrupted by Read (CL=2, BL=4)
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access is allowed.
In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention.
The output is disabled automatically 2 cycle after WRITE assertion.
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
READ
Yb
0
00
Qc0
Qc1
Qc2
Qc3
READ
Ya
0
00
Qa0
Qa1
Qa2
Qb0
READ
Yc
0
10
CLK
Command
A0-9,11-12
A10
BA0-1
DQ
ACT
Xa
Xa
00
Read interrupted by Write (CL=2, BL=4)
READ
Ya
0
00
Qa0
Da0
Da1
Da2
DQM
Write
Ya
0
00
Da3
Output disable by DQM
by WRITE
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