參數(shù)資料
型號(hào): M2V56S20AKT
廠商: Mitsubishi Electric Corporation
英文描述: 256M Synchronous DRAM
中文描述: 256M同步DRAM
文件頁數(shù): 29/49頁
文件大小: 244K
代理商: M2V56S20AKT
Feb.2000
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
29
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70
°
C, unless otherwise noted)
CAPACITANCE
(Ta=0 ~ 70
°
C, Vdd = VddQ = 3.3
±
0.3V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to VssQ
-0.5 ~ VddQ+0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
Ta = 25
°
C
1000
mW
Topr
Operating Temperature
0 ~ 70
°
C
Tstg
Storage Temperature
-65 ~ 150
°
C
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VddQ
Supply Voltage for Output
3.0
3.3
3.6
V
VssQ
Supply Voltage for Output
0
0
0
V
VIH
High-Level Input Voltage all inputs
2.0
Vdd+0.3
V
VIL
Low-Level Input Voltage all inputs
-0.3
0.8
V
VI=1.4v
f=1MHz
VI=25mVrms
Unit
Test Condition
Parameter
Symbol
pF
pF
pF
pF
6.5
4.0
3.5
2.5
3.8
2.5
3.8
2.5
Max.
Min.
Input Capacitance, I/O pin
CI/O
Input Capacitance, CLK pin
CI(K)
Input Capacitance, control pin
CI(C)
Input Capacitance, address pin
CI(A)
Limits
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