參數(shù)資料
型號: M2V28D30ATP-10
廠商: Mitsubishi Electric Corporation
英文描述: 353620600
中文描述: 128M的雙數(shù)據(jù)速率同步DRAM
文件頁數(shù): 23/36頁
文件大小: 1216K
代理商: M2V28D30ATP-10
23
MITSUBISHI ELECTRIC
Jun,'00
Preliminary
MITSUBISHI LSIs
DDR SDRAM (Rev.0.1)
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
After tRCD from the bank activation, a READ command can be issued. 1st Output data is available
after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length
is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8)/A8-A0(x16), and the address
sequence of burst data is defined by the Burst Type. A READ command may be applied to any
active bank, so the row precharge time (tRP) can be hidden behind continuous output data by
interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge
(READA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till
the internal precharge is complete. The internal precharge starts at BL/2 after READA. The next
ACT command can be issued after (BL/2+tRP) from the previous READA.
READ
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK
CLK
Command
A0-9,11
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
READ
Y
0
10
ACT
Xb
Xb
10
PRE
0
00
tRCD
/CAS latency
Burst Length
DQS
Qa0
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
Qb0
Qb1
Qb2
Qb3
Qb4
Qb5
Qb7
Qb8
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M2V28D30ATP-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM
M2V28D40ATP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM
M2V28D40ATP-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM
M2V28S20ATP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM
M2V28S20ATP-6 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM