參數(shù)資料
型號(hào)： M2V28D30ATP-10
廠商： Mitsubishi Electric Corporation
英文描述： 353620600
中文描述： 128M的雙數(shù)據(jù)速率同步DRAM
文件頁數(shù)： 17/36頁
文件大?。?/td> 1216K
代理商： M2V28D30ATP-10
17
MITSUBISHI ELECTRIC
Jun,'00
Preliminary
MITSUBISHI LSIs
DDR SDRAM (Rev.0.1)
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
-75
105
-10
95
x4
x8
110
105
x16
120
115
x4
110
100
x8
115
110
x16
135
130
x4
60
55
x8
65
60
x16
75
70
x4
150
140
x8
170
160
x16
210
200
x4
145
135
x8
165
155
x16
200
180
IDD5
AUTO REFRESH CURRENT: t RC = t RFC (MIN)
x4/x8/x16
190
180
IDD6
SELF REFRESH CURRENT: CKE < 0.2V
x4/x8/x16
3
3
9
x4/x8/x16
40
40
Limits(Max.)
mA
Symbol
Organization
Parameter/Test Conditions
IDD4R
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank active;
Address and control inputs changing once per clock cycle;CL=2.5; t CK = t CK
MIN; IOUT = 0 mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-
down mode; CKE <VIL (MAX); t CK = t CK MIN
x4/x8/x16
IDD2P
IDD2N
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs changing
once per clock cycle
IDD4W
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle; CL=2.5; t CK = t CK
MIN;DQ, DM and DQS inputs changing twice per clock cycle
IDD3P
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; power-
down mode; CKE < VIL (MAX); t CK = t CK MIN
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN); One
bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM and
DQS inputs changing twice per clock cycle; address and other control inputs
changing once per clock cycle
IDD3N
x4/x8/x16
OPERATING CURRENT: One Bank; Active-Precharge; t RC = t RC MIN; t CK
= t CK MIN; DQ, DM and DQS inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
IDD0
IDD1
OPERATING CURRENT: One Bank; Active-Read-Precharge;
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0mA;
Address and control inputs changing once per clock cycle
40
40
Unit
Notes
20
20
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70
o
C, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70
o
C, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
M in.
M ax.
VIH(AC ) High-Level Input Voltage (AC )
VIL(AC )
Low-Level Input Voltage (AC )
VID(AC ) Input Differential Voltage, C LK and /C LK
VIX(AC ) Input C rossing Point Voltage, C LK and /CLK
IO Z
O ff-state O utput C urrent /Q floating Vo=0~VddQ
II
Input C urrent / VIN =0 ~ VddQ
IO H
O utput High C urrent (VO UT = 1.95 V)
IO L
O utput High C urrent (VO UT = 0.35 V)
Vref + 0.35
Vref - 0.35
VddQ + 0.6
0.7
7
8
0.5*VddQ - 0.2 0.5*VddQ + 0.2
-5
-2
-16.8
16.8
5
2
μ
A
μ
A
mA
mA
N otes
Limits
Symbol
Parameter / Test C onditions
Unit
V
V
V
V
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