參數(shù)資料
型號(hào)： M2V12D30TP-75L
廠商： Mitsubishi Electric Corporation
英文描述： 512M Double Data Rate Synchronous DRAM
中文描述： 512M雙數(shù)據(jù)速率同步DRAM
文件頁(yè)數(shù)： 3/38頁(yè)
文件大?。?/td> 754K
代理商： M2V12D30TP-75L
MITSUBISHI
ELECTRIC
-3-
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
Feb. '02
MITSUBISHI LSIs
DDR SDRAM (Rev.1.1)
MITSUBISHI ELECTRIC
PIN FUNCTION
CLK, /CLK
Input
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self refresh.
After self refresh mode is started, CKE becomes asynchronous input. Self refresh
is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12
Input
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11-12(x4) and A0-9,11(x8). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
BA0,1
Input
DQ0-7(x8),
DQ0-3(x4)
Input / Output
DQS
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output pin during Read operation, input during Write operation.
Edge-aligned with read data, placed at the centered of write data to capture
the write data.
SYMBOL
TYPE
DESCRIPTION
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with the input data
during a WRITE operations. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading.
Input / Output
Vref
Input
SSTL_2 reference voltage.
相關(guān)PDF資料
PDF描述
M2S12D20TP-75L 512M Double Data Rate Synchronous DRAM
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M2S12D30TP-75L 512M Double Data Rate Synchronous DRAM
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M2V12D20TP-75 128 x 64 pixel format, LED Backlight available
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