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參數(shù)資料
| 型號： | M2S56D30AKT-75 |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.75 ns, PDSO64 |
| 封裝： | 0.40 MM PITCH, STSOP-64 |
| 文件頁數(shù)： | 16/41頁 |
| 文件大小： | 638K |
| 代理商： | M2S56D30AKT-75 |
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23
DDR SDRAM
E0338M10 (Ver.1.0)
(Previous Rev.1.54E)
Jan. '03 CP(K)
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
M2S56D20/ 30/ 40AKT
Note (Continued) :
20. IDD7 : Operating current is measured under the conditions
(1).Four Bank are being interleaved with tRC(min),burst mode,address and control inputs on NOP edge
are not changing.Iout = 0mA
(2).Timing Patterns
-DDR266B(-75) (133MHz,CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK,
Setup:A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read :A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 -repeat the same timing with random address changing
50% of data changing at every transfer
-DDR266A(-75A) (133MHz,CL=2) : tCK=7.5ns, CL=2, BL=4, tRRD=2*tCK, tRCD=3*tCK,
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 -repeat the same timing with random address changing
50% of data changing at every transfer
-DDR333B(-60) (166MHz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK,
Setup: A0 N A1 RA0 A2 RA1 A3 RA2 N RA3
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 -repeat the same timing with random address changing
50% of data changing at every transfer
*Legend: A=Active,R=Read, RA=Read with Autoprecharge ,P=Precharge, N=DESELECT
21. Low Power Version (-60L/-75AL/-75L)
22. Ultra Low Power Version (-60UL/-75AU/-75UL)
23. For command/address and CK & /CK slew rate > 1.0V/ns.
24. For command/address and CK & /CK slew rate > 0.5V/ns
25. Input Setup & Hold Time Derating for Slew Rate
This derating factor will be used to increase tIS and tIH in the case where the input slew rate is below
0.5V/ns.The input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to
VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
26. I/O Setup & Hold Time Derating for Slew Rate
This derating factor will be used to increase tDS and tDH in the case where the I/O slew rate is below
0.5V/ns.The I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate.
The I/O slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC)
or VIH(DC) to VIL(DC), similarly for rising transitions.
(Notes continued on next page)
I/O Input slew Rate
tDS
tDH
Unit
0.5V/ns
0
ps
0.4V/ns
+75
ps
0.3V/ns
+150
ps
Input slew Rate
tIS
tIH
Unit
0.5V/ns
0
ps
0.4V/ns
+50
ps
0.3V/ns
+100
ps
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2S56D30AKT-75A | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2S56D30AKT-75AL | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2S56D30AKT-75L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2S56D30ATP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
| M2S56D30ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM |
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