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cycle. If the command is used to program in
more than one block then the address must
remain in the starting block as any address that
is not in the same block as the Start Address
terminates the Program operation. The Status
Register Multiple Word Program bit (DQ0) must
be read between each Bus Write cycle to check
that the P/E.C. is ready for the next Word.
3. Finally, after all Words have been programmed,
write one Bus Write operation to any address
outside the block containing the Start Address,
to terminate the programming phase.
The memory is now set to enter the Verify Phase.
Verify Phase.
The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data. If the check fails the P/E.C will
try to reprogram the correct data. The P/E.C will
remain busy until the correct data has been suc-
cessfully programmed. The Verify Phase is man-
datory. If the Verify Phase is not executed the
programmed data cannot be guaranteed.
Three successive steps are required to execute
the Verify Phase of the command.
1. Use one Bus Write operation to latch the Start
Address and the first Word, to be verified. The
Status Register Multiple Word Program bit
(DQ0) should be read to check that the P/E.C. is
ready for the next Word.
2. Each subsequent Word to be verified is latched
with a new Bus Write operation. If any address
that is not in the same block as the Start
Address is given, the Verify operation
terminates. The Status Register Multiple Word
Program (DQ0) must be read to check that the
P/E.C. is ready for the next Word.
3. Finally, after all Words have been verified, write
one Bus Write operation to any address outside
the block containing the Start Address, to
terminate the Verify Phase.
Exit Phase .
Read the Status Register to verify
that DQ6 has stopped toggling. If the Verify Phase
is successfully completed the memory returns to
the Read mode. If the P/E.C. fails to reprogram a
given location, the Verify Phase will terminate and
Error bit DQ5 will be set in the Status Register. If
the error is due to a V
PP
failure DQ4 will also be
set. If the operation fails a Read/Reset command
must be issued to return the device to Read mode.
It is not possible to issue any command to abort or
pause the operation. Typical program times are
given in Table 6. Bus Read operations during the
program operation will output the Status Register
on the Data Inputs/Outputs. See the section on the
Status Register for more details.
Note that the Multiple Word Program command
cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole memory from ’0’ to ’1’.
Block Erase Command.
The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ’1’. All
previous data in the block is lost.
V
PP
must be set to V
HH
during Block Erase. If V
PP
is set to either V
IL
or V
IH
the command will be ig-
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode.
Six Bus Write operations are required to select the
block . The Block Erase operation starts the Pro-
gram/Erase Controller after the last Bus Write op-
eration. The Status Register can be read after the
sixth Bus Write operation. See the Status Register
for details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
During the Block Erase operation the memory will
ignore all commands. Typical block erase times
are given in Table 6. All Bus Read operations dur-
ing the Block Erase operation will output the Sta-
tus Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Chip Erase Command.
The Chip Erase command can be used to erase
the entire memory. It sets all of the bits in the mem-
ory to ’1’. All previous data in the memory is lost.
V
PP
must be set to V
HH
during Chip Erase. If V
PP
is set to either V
IL
or V
IH
the command will be ig-
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode. Six Bus Write
operations are required to issue the Chip Erase
Command and start the Program/Erase Control-
ler.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.