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M29KW016E
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
15., Write AC Characteristics, for details of the tim-
ing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature. The
memory
has
two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
Table 3. Bus Operations
Note: 1. X = VIL or VIH.
2. XX = VIL, VIH or VHH
3. Not necessary for Auto Select or Read/Reset commands.
4. When reading the Status Register during Program or Erase operations, VPP must be kept at VHH.
Operation
E
G
W
VPP
Address Inputs
A0-A19
Data Inputs/Outputs
DQ15-DQ0
Bus Read
VIL
VIH
XX(4)
Cell Address
Data Output
Bus Write
VIL
VIH
VIL
VHH
(3)
Command Address
Data Input
Output Disable
X
VIH
XX
Hi-Z
Standby
VIH
XXX
X
Hi-Z
Read Manufacturer
Code
VIL
VIH
XX
A0 = VIL, A1 = VIL,
Others VIL or VIH
0020h
Read Device Code
VIL
VIH
XX
A0 = VIH, A1 = VIL,
Others VIL or VIH
88ABh