Obsolete
Product(s)
- Obsolete
Product(s)
M29KW016E
8/33
SIGNAL DESCRIPTIONS
See
and
nals connected to this device.
Address Inputs (A0-A19). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs outputs the data stored at the select-
ed address during a Bus Read operation. During
Bus Write operations they represent the com-
mands sent to the Command Interface of the Pro-
gram/Erase Controller.
Data Inputs/Outputs (DQ8-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset (RP). The Reset pin can be used to apply
a Hardware Reset to the memory.
A Hardware Reset is achieved by holding Reset
Low, VIL, for at least tPLPX. After Reset goes High,
VIH, the memory will be ready for Bus Read and
Bus Write operations after tPHEL or tRHEL, which-
ever occurs last. See the Ready/Busy Output sec-
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode and Auto
Select mode. After a Hardware Reset, Bus Read
and Bus Write operations cannot begin until
Ready/Busy becomes high-impedance. See
Tableand
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for Read operations.
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1F capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, ICC3.
VPP Program Supply Voltage. VPP is both a
power supply and Write Protect pin. The two func-
tions are selected by the voltage range applied to
the pin. The Supply Voltage VCC must be applied
before the Program Supply Voltage VPP.
If VPP is in the range 11.4V to 12.6V it acts as a
power supply pin for program and erase opera-
tions. VPP must be stable until the Program/Erase
algorithm is completed.
If VPP is kept in a low voltage range (0V to 3.6V)
VPP is seen as a Write Protect pin. In this case a
voltage lower than VHH gives an absolute protec-
tion against program or erase, while VPP in the
range of VHH enables these functions (see Table Note that VPP must not be left floating or uncon-
nected as the device may become unreliable.
Vss Ground. The VSS Ground is the reference
for all voltage measurements.