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參數(shù)資料
| 型號(hào)： | M29F512B45NZ1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 512 Kbit 64Kb x8, Bulk Single Supply Flash Memory |
| 中文描述： | 512千位64Kb的× 8，散單電源閃存 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 136K |
| 代理商： | M29F512B45NZ1T |
3/16
M29F512B
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1μF capacitor should be connected between
the V
CC
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
CC3
.
Vss Ground.
The V
SS
Ground is the reference
for all voltage measurements.
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 3, Bus Operations, for a summary. Typically
glitches of less than 5ns are ignored by the mem-
ory and do not affect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 7, Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures 8 and 9, Write AC
Waveforms, and Tables 11 and 12, Write AC
Characteristics, for details of the timing require-
ments.
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
2.
Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°C
T
BIAS
Temperature Under Bias
–50 to 125
°C
T
STG
Storage Temperature
–65 to 150
°C
V
IO (2)
Input or Output Voltage
–0.6 to 6
V
V
CC
Supply Voltage
–0.6 to 6
V
V
ID
Identification Voltage
–0.6 to 13.5
V
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